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  february 2008 rev 4 1/226 1 st7foxf1, ST7FOXK1, st7foxk2 8-bit mcu with single voltage flash memory, spi, i2c, adc, timers features memories ? 4 to 8 kbytes single voltage extended flash (xflash) program memory with read-out protection in-circuit programmin g and in-application programming (icp and iap) endurance: 1k write/erase cycles guaranteed data retention: 20 years at 55 c ? 384 bytes ram clock, reset and supply management ? low voltage supervisor (lvd) for safe power-on/off ? clock sources: internal trimmable 8 mhz rc oscillator, auto wakeup internal low power - low frequency oscillator, crystal/ceramic resonato r or external clock ? external reset source and watchdog reset ? five power saving modes: halt, active-halt, auto wakeup from halt, wait and slow i/o ports ? up to 24 multifunctional bidirectional i/os ? up to 8 high sink outputs 6 timers ? configurable watchdog timer ? dual 8-bit lite timers with prescaler, 1 real time base and 1 input capture ? dual 12-bit auto-reload timers with 4 pwm outputs, input capture, output compare, dead-time generation and enhanced one pulse mode functions ? one 16-bit timer communication interfaces: ? i2c multimaster interface ? spi synchronous serial interface a/d converter: up to 10 input channels interrupt management ? 13 interrupt vectors plus trap and reset instruction set ? 8-bit data manipulation ? 63 basic instructions with illegal opcode detection ? 17 main addressing modes ? 8 x 8 unsigned multiply instructions development tools ? full hw/sw development package ? dm (debug module) so20 lqfp32 sdip32 dip20 www.st.com
contents st7foxf1, ST7FOXK1, st7foxk2 2/226 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 register and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 flash programmable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.1 in-circuit programming (icp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.2 in application programming (iap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5.1 read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5.2 flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.6 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.7 description of flash control/status regist er (fcsr) . . . . . . . . . . . . . . . . 28 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.2 index registers (x and y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.3 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.4 condition code register (cc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.5 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1 rc oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.2 customized rc calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.3 auto wakeup rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
st7foxf1, ST7FOXK1, st7foxk2 contents 3/226 6.2 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.1 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2.2 crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2.3 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3.2 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3.3 external power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3.4 internal low voltage detector (lvd) reset . . . . . . . . . . . . . . . . . . . . . . . 42 6.3.5 internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.4.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.5.1 rc calibration control/status register (rcc_csr) . . . . . . . . . . . . . . . . 46 6.5.2 main clock control/status register (mccsr) . . . . . . . . . . . . . . . . . . . 46 6.5.3 rc control register high (rccrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.5.4 rc control register low (rccrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.5.5 prescaler register (pscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.5.6 clock controller control/status register (ckcntcsr) . . . . . . . . . . . . . . 49 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2.1 servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.2.2 interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.4 concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.5 description of interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.5.1 cpu cc register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.5.2 interrupt software priority registers (isprx) . . . . . . . . . . . . . . . . . . . . . . 56 7.5.3 external interrupt control register (eicr) . . . . . . . . . . . . . . . . . . . . . . . 60 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
contents st7foxf1, ST7FOXK1, st7foxk2 4/226 8.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.4.1 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.4.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.5 auto-wakeup from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.5.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.5.2 awufh control/status register (awucsr) . . . . . . . . . . . . . . . . . . . . 70 8.5.3 awufh prescaler register (awupr) . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.2.4 analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.4 unused i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.7 device-specific i/o port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.7.1 standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.7.2 other ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.1.4 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.1.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.1.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.2 dual 12-bit autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.2.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.2.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
st7foxf1, ST7FOXK1, st7foxk2 contents 5/226 10.2.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.2.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.3 lite timer 2 (lt2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 10.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 10.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 10.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 10.3.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.3.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.3.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.4.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 10.4.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.4.6 summary of 16-bit timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.4.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.4.8 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . 139 10.5 i 2 c bus interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.5.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.5.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.6 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.6.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10.6.5 clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.6.6 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.6.7 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.6.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
contents st7foxf1, ST7FOXK1, st7foxk2 6/226 10.6.9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 10.7 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 10.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 10.7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 10.7.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 10.7.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.7.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.7.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.1.1 inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.1.2 immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.1.3 direct modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.1.4 indexed modes (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . 180 11.1.5 indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.1.6 indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.1.7 relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.2.1 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 12 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 12.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 12.3.2 operating conditions with low voltage detector (lvd) . . . . . . . . . . . . 190 12.3.3 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 12.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.4.1 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.4.2 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
st7foxf1, ST7FOXK1, st7foxk2 contents 7/226 12.5 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 194 12.5.1 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 12.5.2 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.6 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.6.1 auto wakeup from halt os cillator (awu) . . . . . . . . . . . . . . . . . . . . . . . 198 12.6.2 crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 199 12.7 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.8 emc (electromagnetic compatibility) charac teristics . . . . . . . . . . . . . . . 201 12.8.1 functional ems (ele ctromagnetic susc eptibility) . . . . . . . . . . . . . . . . . 201 12.8.2 emi (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.8.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 203 12.9 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.9.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.9.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.10 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.10.1 asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.11 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13 device configuration and ordering informati on . . . . . . . . . . . . . . . . . 211 13.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 13.1.1 option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 13.1.2 option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 13.2 device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 st7fox failure analysis service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 13.3.1 starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 13.3.2 development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 13.3.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 13.3.4 order codes for development and programming tools . . . . . . . . . . . . . 215 13.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 14 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 14.1 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
list of tables st7foxf1, ST7FOXK1, st7foxk2 8/226 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2. device pin description (32-pin packages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3. device pin description (20-pin package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4. hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5. flash register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. interrupt software priority truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7. predefined rc oscillator ca libration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8. st7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 9. cpu clock delay during reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 10. reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 11. internal rc prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 12. clock register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 13. interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 14. setting the interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 15. interrupt vector vs isprx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 16. dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 17. st7foxf1/ST7FOXK1 interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 18. st7foxk2 interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 19. interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 20. enabling/disabling active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 21. configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 22. awu register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 23. dr value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 24. i/o port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 25. st7foxf1/ST7FOXK1/st7foxk2 i/o port configuration . . . . . . . . . . . . . . . . . . . . . . . . 75 table 26. effect of low power modes on i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 table 27. description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 28. pa5:0, pb7:0, pc7:4 and pc2:0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 29. pa7:6 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 30. pc3 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 31. port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 32. i/o port register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 33. watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 34. watchdog timer register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 35. effect of low power modes on autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 36. description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 37. counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 38. register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 table 39. effect of low power modes on lite timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 40. description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 41. lite timer register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 42. effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 43. 16-bit timer interrupt control/wa keup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 44. summary of 16-bit timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 45. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 46. effect of low power modes on the i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 47. description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 48. configuration of i 2 c delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
st7foxf1, ST7FOXK1, st7foxk2 list of tables 9/226 table 49. i 2 c register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 50. low power mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 51. interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 52. spi master mode sck frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 53. spi register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 54. effect of low power modes on the a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 55. channel selection using ch[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 56. configuring the adc clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 77 table 57. adc register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 58. description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 78 table 59. st7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 table 60. instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 61. instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . 180 table 62. instructions supporting direct, indexed, in direct and indirect indexed addressing modes 181 table 63. instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 table 64. st7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 65. illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 66. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 67. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 68. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 69. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 70. operating characteristics with lvd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 71. internal rc oscillator characteristics (5.0 v calibra tion) . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 72. supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 73. on-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 74. i 2 c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 75. scl frequency (multimaster i 2 c interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 76. spi interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 77. general timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 78. external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 79. awu from halt characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 80. crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 81. ram and hardware registers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 82. flash program memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 83. ems test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 84. emi emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 85. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 table 86. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 87. general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 88. output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 89. asynchronous reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 90. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 91. adc accuracy with vdd = 4.5 to 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 92. startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 93. selection of the resonator oscilla tor range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 94. configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 95. development tool order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 96. st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 97. 20-pin plastic small outline package, 300-mil width, mechanical data . . . . . . . . . . . . . . . 220 table 98. 20-pin plastic dual in-line package, 300-mil width, mechanical data . . . . . . . . . . . . . . . . 221 table 99. 32-pin plastic dual in-line package, shrink 400-mil width, mechanical data . . . . . . . . . . . 222 table 100. 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . . . . . . . . 223
list of tables st7foxf1, ST7FOXK1, st7foxk2 10/226 table 101. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 102. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
st7foxf1, ST7FOXK1, st7foxk2 list of figures 11/226 list of figures figure 1. general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2. 32-pin sdip package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. 32-pin lqfp 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. 20-pin so and dip package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 5. st7foxf1/ST7FOXK1/st7foxk2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6. typical icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 8. stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 9. rccrh_user and rccrl_user programming flowchart . . . . . . . . . . . . . . . . . . . . . . . 35 figure 10. rc user calibration programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 figure 11. clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 12. clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 figure 13. reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 14. reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 15. reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 16. low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17. reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 18. interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 19. priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 20. concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 21. nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 22. power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 23. slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 24. wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 25. active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 26. active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 27. halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 28. halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 29. awufh mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 30. awuf halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 31. awufh mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 32. i/o port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 33. interrupt i/o port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 34. watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 35. single timer mode (encntr2=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 figure 36. dual timer mode (encntr2=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 37. pwm polarity inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 38. pwm function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 39. pwm signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 40. dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 41. st7foxf1/ST7FOXK1 block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 42. st7foxk2 block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 43. block diagram of output compare mode (single timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 44. block diagram of input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 45. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 46. long range input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 47. long range input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 48. block diagram of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
list of figures st7foxf1, ST7FOXK1, st7foxk2 12/226 figure 49. one pulse mode and pwm timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 50. dynamic dcr2/3 update in one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 51. force overflow timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 52. lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 53. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 54. watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 55. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 56. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 57. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 58. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 59. counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 60. input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 61. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 62. output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 63. output compare timing diagram, f timer =f cpu /2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 64. output compare timing diagram, f timer =f cpu /4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 65. one pulse mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 66. one pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 29 figure 67. pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 68. pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 69. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 70. i 2 c interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 71. transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 72. event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 73. serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 figure 74. single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 75. generic ss timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 76. hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 77. data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 78. clearing the wcol bit (wri te collision flag) so ftware sequence . . . . . . . . . . . . . . . . . . . . 166 figure 79. single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 80. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 81. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 figure 82. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 83. spi slave timing diagram with cpha=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 84. spi slave timing diagram with cpha=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 85. spi master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 86. typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 figure 87. typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 199 figure 88. two typical applications with unused i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 89. reset pin protection when lvd is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 90. reset pin protection when lvd is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 91. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 92. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 93. st7foxf1/ST7FOXK1/st7foxk2 ordering information scheme . . . . . . . . . . . . . . . . . 214 figure 94. 20-pin plastic small outline package, 300-mil width, package outline. . . . . . . . . . . . . . . . 220 figure 95. 20-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 221 figure 96. 32-pin plastic dual in-line package, shrink 400-mil width, package outline. . . . . . . . . . . . 222 figure 97. 32-pin low profile quad flat package (7x7), package outline . . . . . . . . . . . . . . . . . . . . . . . 223
st7foxf1, ST7FOXK1, st7foxk2 description 13/226 1 description the st7fox is a member of the st7 microcontroller family. all st7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. the device is positioned at the entry level of the 8-bit microcontroller range providing an attractive cost while at the same time embedding the most advanced features. the st7fox features flash memory with byte-by-byte in-circuit programming (icp) and in- application programm ing (iap) capability. under software control, the st7fox device can be placed in wait, slow, or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling th e design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. the st7fox features an on-chip debug module (dm) to support in-circuit debugging (icd). for a description of the dm registers, refer to the st7 icc protocol reference manual. table 1. device summary features st7foxf1 / ST7FOXK1 st7foxk2 program memory - bytes 4k 8k ram (stack) - bytes 384 (128) timers dual 8-bit timer, dual 12-bit at (4 pwm) dual 8-bit timer, dual 12-bit at (4 pwm), 1 x 16-bit timer adc 1 x 10-bit peripherals i2c i2c and spi packages dip20, so20, lqfp32, sdip32 lqfp32, sdip32
description st7foxf1, ST7FOXK1, st7foxk2 14/226 figure 1. general block diagram 8-bit core alu address and data bus osc1 osc2 reset port a internal clock control ram pa7:0 (8 bits) v ss v dd power supply flash (4 to 8 kbytes) memory ext. 1 mhz int. rc osc 8-bit dual lite timer port b pb7:0 (8 bits) i 2 c 8 mhz osc to 16 mhz 10-bit adc 12-bit auto-reload clkin / 2 watchdog debug module port c pc7:0 (8 bits) program / 2 int. 32 khz dual timer rc osc spi 1) 16-bit timer 1) note 1 : available on 8k version only (384 bytes) lvd
st7foxf1, ST7FOXK1, st7foxk2 pin description 15/226 2 pin description figure 2. 32-pin sdip package pinout figure 3. 32-pin lqfp 7x7 package pinout 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 ei1 eix associated external interrupt vector (hs) 20ma high sink capability atpwm0/pa2(hs) break1/pc7 ocmp1_a 1) /pa0(hs) atic/pa1(hs) atpwm1/pa3(hs) i2cclk/pa7(hs) reset atpwm3/pa5(hs) atpwm2/mco/pa4(hs) i 2 c data / pa 6 ( h s ) v dda pb0/ain0 pb1/ain1/clkin v ss osc1/clkin osc2 v ssa pb2/ain2 v dd pb3/ain3/mosi 1) pc1/ain9/icap2_a 1) pc0/ain8/icap1_a 1) pb7/ain7/ss /ocmp2_a 1) pb6/ain6/sck 1) pb5/ain5/extclk_a 1) pb4/ain4/miso 1) pc6 pc5/break2 pc4/ltic pc3/iccclk pc2/iccdata nc ei2 ei0 ei2 ei2 note 1: available on 8k version only v ssa v dda ain0/pb0 clkin/ain1/pb1 ain2/pb2 v ss osc1/clkin osc2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10111213141516 1 2 3 4 5 6 7 8 pb6/ain6/sck pb5/ain5/extclk_a pb4/ain4/miso pb3/ain3/mosi pc2/iccdata pc1/ain9/icap2_a pc0/ain8/icap1_a pb7/ain7/ss /ocmp2_a pc6 pc5/break2 pc4/ltic pc3/iccclk pa 2 ( h s ) / at p w m 0 pa 1 ( h s ) / at i c pa0(hs)/ocmp1_a pc7/break1 eix associated external interrupt vector (hs) 20ma high sink capability i2cclk/pa7(hs) reset atpwm2/mco/pa4(hs) i2cdata/pa6(hs) v dd nc atpwm3/pa5(hs) atpwm1/pa3(hs) ei0 ei2 ei1
pin description st7foxf1, ST7FOXK1, st7foxk2 16/226 legend / abbreviations for ta b l e 2 : type: i = input, o = output, s = supply in/output level: c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20 ma high sink (on n-buffer only) port and control configuration: input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog output: od = open drain, pp = push-pull the reset configuration of each pin is shown in bold which is valid as long as the device is in reset state. table 2. device pin description (32-pin packages) pin number pin name type level port/control main function (after reset) alternate function lqfp32 sdip32 input output input output float wpu int ana od (1) pp 1 5 pa 3 ( h s ) / at p w m 1 i / o c t hs x ei0 xx port a3 (hs) at p w m 1 26 pa 4 ( h s ) / at p w m 2 / m c o i/o c t hs x xx port a4 (hs) at p w m 2 / mco 3 7 pa 5 ( h s ) at p w m 3 i / o c t hs x xx port a5 (hs) at p w m 3 48 pa 6 ( h s ) / i2cdata/sck (2) i/o c t hs x ei0 t port a6 (hs) i2cdata/spi serial clock 59 pa7(hs)/i2cclk/ss (2) i/o c t hs x t port a7 (hs) i2cclk/spi slave select (active low) 6 10 reset x x reset 812 v dd (3) s digital supply voltage 913 v ss (3) s digital ground voltage 10 14 osc1/clkin i resonator oscillator inverter input or external clock input 11 15 osc2 o resonator oscillator output 12 16 v ssa (3) s analog ground voltage 13 17 v dda (3) s analog supply voltage
st7foxf1, ST7FOXK1, st7foxk2 pin description 17/226 14 18 pb0/ain0 i/o c t x ei1 xxx port b0 ain0 15 19 pb1/ain1/clkin i/o c t x xxx port b1 ain1/externa l clock source 16 20 pb2/ain2 i/o c t x xxx port b2 ain2 17 21 pb3/ain3/mosi (2) i/o c t x xxx port b3 ain3/spi master out /slave in data 18 22 pb4/ain4/miso (2) i/o c t x xxx port b4 ain4/spi master in/slave out data 19 23 pb5/ain5/ extclk_a (2) i/o c t x xxx port b5 ain5/timer a input clock 20 24 pb6/ain6/sck (2) i/o c t x xxx port b6 ain6/spi serial clock 21 25 pb7/ain7/ss (2) / ocmp2_a (2) i/o c t x xxx port b7 ain7/spi slave select (active low)/ timer a output compare 2 22 26 pc0/ain8/ icap1_a (2) i/o c t x ei2 xxx port c0 ain8/timer a input capture 1 23 27 pc1/ain9/ icap2_a (2) i/o c t x xxx port c1 ain9/timer a input capture 2 24 28 pc2/iccdata i/o c t x xx port c2 iccdata 25 29 pc3/iccclk i/o c t x x xx port c3 iccclk 26 30 pc4/ltic i/o c t x ei2 xx port c4 lt i c 27 31 pc5/break2 (4) i/o c t x xx port c5 break2 28 32 pc6 i/o c t x xx port c6 29 1 pc7/break1 i/o c t x xx port c7 break1 table 2. device pin description (32-pin packages) (continued) pin number pin name type level port/control main function (after reset) alternate function lqfp32 sdip32 input output input output float wpu int ana od (1) pp
pin description st7foxf1, ST7FOXK1, st7foxk2 18/226 figure 4. 20-pin so and dip package pinout legend / abbreviations for ta b l e 3 : type: i = input, o = output, s = supply in/output level:c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog output: od = open drain, pp = push-pull note: the reset configuration of ea ch pin is shown in bold which is valid as long as the device is in reset state. 30 2 pa 0 (hs) (5) /ocmp1_a (2) i/o c t hs (5) x ei0 xx port a0 (hs) (5) / timer a output compare 1 31 3 pa1 (hs)/atic i/o c t hs x xx port a1 (hs) at i c 32 4 pa2 (hs)/atpwm0 i/o c t hs x xx port a2 (hs) at p w m 0 1. in the open-drain output column, t defines a true open-drain i/o (p-buffer and protection diode to v dd are not implemented). 2. available on st7foxk2 only. 3. it is mandatory to connect all available v dd and v dda pins to the supply voltage and all v ss and v ssa pins to ground. 4. break2 available on st7foxk2 only 5. available on ST7FOXK1 only. table 2. device pin description (32-pin packages) (continued) pin number pin name type level port/control main function (after reset) alternate function lqfp32 sdip32 input output input output float wpu int ana od (1) pp 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 (hs) 20ma high sink capability eix associated external interrupt vector 12 11 9 10 ei2 i 2 c data / pa 6 ( h s ) pc4/ltic pc3/iccclk pc2/iccdata i2cclk/pa7(hs) reset v ss pb0/ain0 pb1/ain1/clkin pb2/ain2 pb3/ain3 pb4/ain4 atpwm1/pa3(hs) atpwm2/mco/pa4(hs) atpwm3/pa5(hs) ei1 atic/pa1(hs) atpwm0/pa2(hs) v dd pb5/ain5 pc6 ei0 ei2 ei2
st7foxf1, ST7FOXK1, st7foxk2 pin description 19/226 table 3. device pin description (20-pin package) pin number pin name type level port / control main function (after reset) alternate function input output input output (1) float wpu int ana od pp 1 pc6 i/o c t x ei2 x x port c6 2 pa1 (hs)/atic i/o c t hs x ei0 x x port a1 (hs) atic 3 pa2 (hs)/atpwm0 i/o c t hs x x x port a2 (hs) atpwm0 4 pa3 (hs)/atpwm1 i/o c t hs x x x port a3 (hs) atpwm1 5 pa 4 (hs)atpwm2/mco i/o c t hs x x x port a4 (hs) atpwm2/mco 6 pa5 (hs)atpwm3 i/o c t hs x x x port a5 (hs) atpwm3 7 pa6 (hs)/i2cdata i/o c t hs x t port a6 (hs) i2cdata 8 pa7 (hs)/ i2cclk i/o c t hs x t port a7 (hs) i2cclk 9 reset x x reset 10 v ss (3) s digital ground voltage 11 v dd (2) s digital supply voltage 12 pb0/ain0 i/o c t x ei1 x x x port b0 ain0 13 pb1/ain1/clkin i/o c t xxxxport b1 ain1/external clock source 14 pb2/ain2 i/o c t x x x x port b2 ain2 15 pb3/ain3 i/o c t x x x x port b3 ain3 16 pb4/ain4 i/o c t x x x x port b4 ain4 17 pb5/ain5 i/o c t x x x x port b5 ain5 18 pc2/iccdata i/o c t x ei2 x x port c2 iccdata 19 pc3/iccclk i/o c t x x x port c3 iccclk 20 pc4/ltic i/o c t x ei2 x x port c4 ltic 1. in the open-drain output column, t defines a true open-drain i/o (p-buffer and protection diode to v dd not implemented). 2. it is mandatory to connect all available v dd and v dda pins to the supply voltage and all v ss and v ssa pins to ground.
register and memory mapping st7foxf1, ST7FOXK1, st7foxk2 20/226 3 register and memory mapping as shown in figure 5 , the mcu is capable of addressing 64 kbytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, 384 bytes of ram and 4 to 8 kbytes of flash program memory. the ram space includes up to 128 bytes for the stack from 180h to 1ffh. the highest address bytes contain the user reset and interrupt vectors. the flash memory contains two sectors (see figure 5 ) mapped in the upper part of the st7 addressing space so the reset and interrupt vectors are located in sector 0 (ffe0h-ffffh). the size of flash sector 0 and other device options are configurable by option bytes (refer to section 13.1 on page 211 ). caution: memory locations marked as ?reserved? mu st never be accessed . accessing a reserved area can have unpredictable effects on the device. figure 5. st7foxf1/ST7FOXK1/st7foxk2 memory map 0000h flash memory interrupt & reset vectors hw registers 0080h 007fh (see ta bl e 8 ) ffe0h ffffh (see table 17 ) reserved short addressing ram (zero page) 0080h 00ffh e000h dfffh ffdfh 128 bytes stack 0100h 017fh 8 or 4 kbytes dee0h see section 6.1.1 01ffh 0200h ram ram (384 bytes) 0180h 01ffh dee1h rccrh rccrl e000h (4 kbytes) (8 kbytes) f000h efffh f800h f7ffh flash program memory (4 kbytes) sector 1 sector 0 (2 kbytes) (1 kbyte) (0.5 kbyte) ffffh 1000h 1001h reserved rccrh_user rccrl_user
st7foxf1, ST7FOXK1, st7foxk2 register and memory mapping 21/226 table 4. hardware register map (1) address block register label register name reset status remarks 0000h 0001h 0002h port a pa d r pa d d r pa o r port a data register port a data direction register port a option register 00h 00h 00h r/w r/w r/w 0003h 0004h 0005h port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 00h 00h r/w r/w r/w 0006h 0007h 0008h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h 00h 08h r/w r/w r/w 0009h to 000bh reserved area (3 bytes) 000ch 000dh 000eh 000fh 0010h lite timer ltcsr2 lta r r ltcntr ltcsr1 lt i c r lite timer control/status register 2 lite timer auto-reload register lite timer counter register lite timer control/status register 1 lite timer input capture register 0fh 00h 00h 0x00 0000b xxh r/w r/w read only r/w read only 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002ah auto- reload timer at c s r cntr1h cntr1l at r 1 h at r 1 l pwmcr pwm0csr pwm1csr pwm2csr pwm3csr dcr0h dcr0l dcr1h dcr1l dcr2h dcr2l dcr3h dcr3l aticrh at i c r l atcsr2 breakcr1 at r 2 h at r 2 l dtgr breaken timer control/status register counter register 1 high counter register 1 low auto-reload register 1 high auto-reload register 1 low pwm output control register pwm 0 control/status register pwm 1 control/status register pwm 2 control/status register pwm 3 control/status register pwm 0 duty cycle register high pwm 0 duty cycle register low pwm 1 duty cycle register high pwm 1 duty cycle register low pwm 2 duty cycle register high pwm 2 duty cycle register low pwm 3 duty cycle register high pwm 3 duty cycle register low input capture register high input capture register low timer control/status register 2 break control register auto-reload register 2 high auto-reload register 2 low dead time generation register break enable register 0x00 0000b 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h 03h r/w read only read only r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w read only read only r/w r/w r/w r/w r/w r/w 002bh reserved area (1 byte) 002ch auto- reload timer breakcr2 (4) break control register 2 (4) 00h r/w
register and memory mapping st7foxf1, ST7FOXK1, st7foxk2 22/226 002dh 002eh 002fh 0030h 0031h itc ispr0 ispr1 ispr2 ispr3 eicr interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 external interrupt control register ffh ffh ffh ffh 00h r/w r/w r/w r/w r/w 0032h reserved area (1 byte) 0033h wdg wdgcr watchdog control register 7fh r/w 0034h flash fcsr flash control/status register 00h r/w 0035h rc calibration rcc_csr rc calibration control/status register 00h r/w 0036h 0037h 0038h adc adccsr adcdrh adcdrl a/d control status register a/d data register high a/d data low / test register 00h xxh 0xh r/w read only r/w 0039h reserved area (1 byte) 003ah mcc mccsr main clock cont rol/status register 00h r/w 003bh 003ch 003dh clock and reset rccrh rccrl pscr rc oscillator control register high rc oscillator control register low prescaler register ffh 011x 0x00b 00h or 03h (2) r/w r/w r/w 003eh to 0047h reserved area (10 bytes) 0048h 0049h awu awucsr awupr awu control/status register awu preload register ffh 00h r/w r/w 004ah 004bh 004ch 004dh 004eh 004fh 0050h dm (3) dmcr dmsr dmbk1h dmbk1l dmbk2h dmbk2l dmcr2 dm control register dm status register dm breakpoint register 1 high dm breakpoint register 1 low dm breakpoint register 2 high dm breakpoint register 2 low dm control register 2 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w 0051h clock controller ckcntcsr clock controller status register 09h r/w 0052h to 0054h reserved area (3 bytes) table 4. hardware register map (1) (continued) address block register label register name reset status remarks
st7foxf1, ST7FOXK1, st7foxk2 register and memory mapping 23/226 0055h 0056h 0057h 0058h 0059h 005ah 005bh 005ch 005dh 005eh 005fh 0060h 0061h 0062h 0063h 16-bit timer (4) tac r 2 tac r 1 tac s r ta i c h r 1 ta i c l r 1 taochr1 tao c l r 1 tachr tac l r taachr ta ac l r ta i c h r 2 ta i c l r 2 taochr2 tao c l r 2 timer a control register 2 timer a control register 1 timer a control/status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a output counter high register timer a output c ounter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h 00h xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0064h 0065h 0066h 0067h 0068h 0069h 006ah i2c i2ccr i2csr1 i2csr2 i2cccr i2coar1 i2coar2 i2cdr i 2 c control register i 2 c status register 1 i 2 c status register 2 i 2 c clock control register i 2 c own address register 1 i 2 c own address register 2 i 2 c data register 00h 00h 00h 00h 00h 40h 00h r/w read only read only r/w r/w r/w r/w 0070h 0071h 0072h spi (4) spidr spicr spisr spi data register spi control register spi status register 0xh 00h xxh r/w r/w r/w 1. legend: x=undefined, r/w=read/write. 2. reset status is 03h for st7foxk2 and 00h for st7foxf1 and ST7FOXK1 3. for a description of the debug module regi sters, see icc protocol reference manual. 4. available on st7foxk2 only table 4. hardware register map (1) (continued) address block register label register name reset status remarks
flash programmable memory st7foxf1, ST7FOXK1, st7foxk2 24/226 4 flash programmable memory 4.1 introduction the st7 single voltage extended flash (xflash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. the xflash devices can be programmed off-board (plugged in a programming tool) or on- board using in-circuit programming or in-application programming. the array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features icp (in-circuit programming) iap (in-application programming) ict (in-circuit testing) for downloading and executing user application test patterns in ram sector 0 size configurable by option byte read-out and write protection 4.3 programming modes the st7 can be programmed in three different ways: insertion in a programming tool. in this mode, flash sectors 0 and 1, option byte row can be programmed or erased. in-circuit programming. in this mode, flash sectors 0 and 1, option byte row can be programmed or erased without removing the device from the application board. in-application programming. in this mode, sector 1 can be programmed or erased without removing the device from the application board and while the application is running. 4.3.1 in-circuit programming (icp) icp uses a protocol called icc (in-circuit communication) which allows an st7 plugged on a printed circuit board (pcb) to communicate with an external programming device connected via cable. icp is performed in three steps: switch the st7 to icc mode (in- circuit communications). this is done by driving a specific signal sequence on the iccclk/data pins while the reset pin is pulled low. when the st7 enters icc mode, it fetches a specific reset vector which points to the st7 system memory containing the icc protocol routine. this routine enables the st7 to receive bytes from the icc interface. download icp driver code in ram from the iccdata pin execute icp driver code in ram to program the flash memory
st7foxf1, ST7FOXK1, st7foxk2 flash programmable memory 25/226 depending on the icp driver code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 in applicati on programming (iap) this mode uses an iap driver program previously programmed in sector 0 by the user (in icp mode). this mode is fully controlled by user software. this allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) iap mode can be used to program any memory areas except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.4 icc interface icp needs a minimum of 4 and up to 6 pins to be connected to the programming tool. these pins are: reset : device reset v ss : device power supply ground iccclk: icc output serial clock pin iccdata: icc input serial data pin osc1: main clock input for external source v dd : application board power supply (optional, see note 3) note: 1 if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programmin g tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. refer to the programming tool documentation for recommended resistor values. 2 during the icp session, the programming tool must control the reset pin. this can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1 k ? ). a schottky diode can be used to isolate the application reset circuit in this case. when using a classical rc network with r>1 k ? or a reset management ic with open drain output and pull-up resistor>1 k ? , no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3 the use of pin 7 of the icc connector depend s on the programming tool architecture. this pin must be connected when using most st programming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4 in ?enabled option byte? mode (38-pulse icc mode), th e internal rc oscillator is forced as a clock source, regardless of the selection in the option byte. in ?disabled option byte? mode (35-pulse icc mode), pin 9 has to be connected to the pb1/clkin pin of the st7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. caution: during normal operation the iccclk pin must be internally or externally pulled- up (external pull-up of 10 k ? mandatory in noisy environment) to avoid entering icc mode unexpectedly
flash programmable memory st7foxf1, ST7FOXK1, st7foxk2 26/226 during a reset. in the application, even if the pin is configured as output, any reset will put it back in input pull-up. figure 6. typical icc interface programming tool icc connector iccdata iccclk reset vdd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 icc connector application board icc cable (see note 3) st7 pb1/clkin optional see note 1 see note 1 and caution see note 2 application reset source application i/o (see note 4)
st7foxf1, ST7FOXK1, st7foxk2 flash programmable memory 27/226 4.5 memory protection there are two different types of memory protection: read-out protection and write/erase protection which can be applied individually. 4.5.1 read-out protection read-out protection, when selected provides a protection against program memory content extraction and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. in flash devices, this protection is remove d by reprogramming the option. in this case, the program memory is automatically erased and the device can be reprogrammed. the read-out protection is enabled and removed through the fmp_r bit in the option byte. 4.5.2 flash write/erase protection write/erase protection, when set, makes it impossible to both overwrite and erase program memory. its purpose is to provide advanced security to applications and prevent any change being made to the memory content. write/erase protection is enabled through the fmp_w bit in the option byte. caution: once set, write/erase protection can never be removed. a write-protected flash device is no longer reprogrammable. 4.6 related documentation for details on flash programming and icc pr otocol, refer to the st7 flash programming reference manual and to the st7 icc protocol reference manual .
flash programmable memory st7foxf1, ST7FOXK1, st7foxk2 28/226 4.7 description of flash control/status register (fcsr) this register controls the xflash erasing and programming using icp, iap or other programming methods. 1st rass key: 0101 0110 (56h) 2nd rass key: 1010 1110 (aeh) when an epb or another programm ing tool is used (in socket or icp mode), the rass keys are sent automatically. reset value: 000 0000 (00h) 7 0 00000optlatpgm read/write table 5. flash register mapping and reset values address (hex.) register label 76543210 0034 fcsr reset value - 0 - 0 - 0 - 0 - 0 opt 0 lat 0 pgm 0
st7foxf1, ST7FOXK1, st7foxk2 central processing unit 29/226 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 5.2 main features 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes two 8-bit index registers 16-bit stack pointer low power modes maskable hardware interrupts non-maskable software interrupt 5.3 cpu registers the six cpu registers shown in figure 7 . they are not present in the memory mapping and are accessed by specific instructions. figure 7. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value
central processing unit st7foxf1, ST7FOXK1, st7foxk2 30/226 5.3.1 accumulator (a) the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 5.3.2 index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the following instruction refers to the y register.) the y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). 5.3.3 program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). 5.3.4 condition co de register (cc) the 8-bit condition code register contains the interrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop instructions. reset value: 111x 1xxx these bits can be individually tested and/or controlled by specific instructions. arithmetic management bits bit 4 = h half carry bit this bit is set by hardware when a carry occurs between bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruction. the h bit is useful in bcd arithmetic subroutines. 7 0 11i1hi0nzc read/write
st7foxf1, ST7FOXK1, st7foxk2 central processing unit 31/226 bit 3 = i interrupt mask bit this bit is set by hardware when entering in interrupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret instructions and is tested by the jrm and jrnm instructions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptible because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. bit 2 = n negative bit this bit is set and cleared by hardware. it is representative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (that is, the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instructions. bit 1 = z zero bit this bit is set and cleared by hardware. this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow bit this bit is set and cleared by hardware and software. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. interrupt management bits bits 5,3 = i1, i0 interrupt bits the combination of the i1 and i0 bits gives the current interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (ixspr). they can be also set/cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see section 9.6: interrupts for more details.
central processing unit st7foxf1, ST7FOXK1, st7foxk2 32/226 * 5.3.5 stack pointer (sp) reset value: 01ffh the stack pointer is a 16-bit register which is always pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 8 ). since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer contains its reset value (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. the previously stored information is then overwritten and therefore lost. the stack also wraps in case of an underflow. the stack is used to save the return address during a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 8 . when an interrupt is received, the sp is decremented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an interrupt five locations in the stack area. table 6. interrupt software priority truth table interrupt software priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 15 8 7 0 0 0 0 0 0 0 0 1 1 sp6 sp5 sp4 sp3 sp2 sp1 sp0 read/write
st7foxf1, ST7FOXK1, st7foxk2 central processing unit 33/226 figure 8. stack manipulation example pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0180h stack higher address = 01ffh stack lower address = 0180h
supply, reset and clock management st7foxf1, ST7FOXK1, st7foxk2 34/226 6 supply, reset and clock management the device includes a range of utility featur es for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. the main features are the following: clock management ? 8 mhz internal rc oscillator (enabled by option byte) ? auto wakeup rc oscillator (enabled by option byte) ? 1 to 16 mhz or 32 khz external crystal/ceramic resonator (selected by option byte) ? external clock input (enabled by option byte) reset sequence manager (rsm) system integrity management (si) ? main supply low voltage detection (lvd) with reset generation (enabled by option byte) 6.1 rc oscillator adjustment 6.1.1 internal rc oscillator the device contains an internal rc oscillator with a specific accuracy for a given device, temperature and voltage range (4.5 v - 5.5 v). it must be calibrated to obtain the frequency required in the application. this is done by software writing a 10-bit calibration value in the rccrh (rc control register high) and in the bi ts 6:5 in the rccrl (rc control register low). whenever the microcontroller is reset, the rccr returns to its default value (ffh), i.e. each time the device is reset, the calibration value must be loaded in the rccr. predefined calibration values are stored for 5 v v dd supply voltage at 25 c (see ta bl e 7 ). in 38-pulse icc mode, the internal rc oscillato r is forced as a clock source, regardless of the selection in the option byte. section 12: electrical characteristics on page 187 for more information on the frequency and accuracy of the rc oscillator. to improve clock stability and frequency accura cy, it is recommended to place a decoupling capacitor, typically 100 nf, between the v dd and v ss pins and also between the v dda and v ssa pins as close as possible to the st7 device. table 7. predefined rc oscillator calibration values rccr conditions st7fox address rccrh v dd = 5v t a = 25c f rc = 8 mhz dee0h (1) (cr[9:2]) 1. the dee0h and dee1h addresses are located in a rese rved area in non-volatile memory. they are read- only bytes for the application code. this area cannot be erased or programmed by any icc operations. for compatibility reasons with the rccrl register, cr[ 1:0] bits are stored in the 5th and 6th position of dee1 address. rccrl dee1h (1) (cr[1:0])
st7foxf1, ST7FOXK1, st7foxk2 supply, reset and clock management 35/226 these bytes are systematically programmed by st. 6.1.2 customized rc calibration if the application requires a higher frequency accuracy or if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. two non- volatile bytes (rccrh_user and rccrl_user ) are reserved for storing these new values. these two-byte area is electrically erasable programmable read only memory. note: refer to application note an1324 for information on how to calibrate the rc frequency using an external reference signal. how to program rccrh_user and rccrl_user to access the write mode, the rcclat bit has to be set by software (the rccpgm bit remains cleared). when a write access to this two-byte area occurs, the values are latched. when rccpgm bit is set by the software, the latched data are programmed in the eeprom cells. to avoid wrong programming, the us er must take care to only access these two-byte addresses. at the end of the programming cycle, the rccpgm and rcclat bits are cleared simultaneously. note: during the programming cycle, it is forbidden to access the latched data (see figure 9 ). figure 9. rccrh_user and rccrl _user programming flowchart note: if a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. access error handling if a read access o ccurs while rcclat=1, then the data bus will not be driven. if a write access occurs while rcclat=0, th en the data on the bus will not be latched. read mode rcclat=0 rccpgm=0 write mode rcclat=1 rccpgm=0 read bytes write the 2 bytes at their address start programming cycle rcclat=1 rccpgm=1 (set by software) rcclat 01 cleared by hardware
supply, reset and clock management st7foxf1, ST7FOXK1, st7foxk2 36/226 if a programming cycle is interrupted (by a reset action), the integrity of the data in memory will not be guaranteed. caution: when the read-out protection is enabled through an option bit (see section 13.1: option bytes ), these two bytes are protected against read- out (including a re-write protection). in flash devices, when this protection is remove d by reprogramming the option byte, these two bytes are automatically erased. figure 10. rc user calibration programming cycle 6.1.3 auto wakeup rc oscillator the st7fox also contains an auto wakeup rc oscillator. this rc oscillator should be enabled to enter auto wakeup from halt mode. the auto wakeup (awu) rc oscillator can also be configured as the startup clock through the cksel[1:0] opt ion bits (see section 13.1: option bytes on page 211 ). this is recommended for app lications where very low power consumption is required. switching from one startup clock to another can be done in run mode as follows (see figure 11 ): case 1 switching from internal rc to awu 1. set the rc/awu bit in the ckcntcsr register to enable the awu rc oscillator 2. the rc_flag is cleared and the clock output is at 1. 3. wait 3 awu rc cycles till the awu_flag is set 4. the switch to the awu clock is made at the positive edge of the awu clock signal 5. once the switch is made, the internal rc is stopped rcclat erase cycle write cycle rccpgm t prog read operation not possible write of data latches read operation possible internal programming voltage byte 1 byte 2 t prog is typically 5 ms and max 10 ms
st7foxf1, ST7FOXK1, st7foxk2 supply, reset and clock management 37/226 case 2 switching from awu rc to internal rc 1. reset the rc/awu bit to enable the internal rc oscillator 2. using a 4-bit counter, wait until 8 intern al rc cycles have elapsed. the counter is running on internal rc clock. 3. wait till the awu_flag is cleared (1aw u rc cycle) and the rc_flag is set (2 rc cycles) 4. the switch to the internal rc clock is made at the positive edge of the internal rc clock signal 5. once the switch is made, the awu rc is stopped note: 1 when the internal rc is not selected, it is stopped so as to save power consumption. 2 when the internal rc is selected, the awu rc is turned on by hardware when entering auto wakeup from halt mode. 3 when the external clock is selected , the awu rc oscillator is always on. figure 11. clock switching internal rc awu rc set rc/awu poll awu_flag until set internal rc reset rc/awu poll rc_flag until set awu rc
supply, reset and clock management st7foxf1, ST7FOXK1, st7foxk2 38/226 figure 12. clock management block diagram 6.2 multi-oscillator (mo) the main clock of the st7 can be generated by four different source types coming from the multi-oscillator block (1 to 16 mhz): an external source 5 different configurations for crys tal or ceramic resonator oscillators an internal high frequency rc oscillator each oscillator is optimized fo r a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in ta bl e 8 . refer to the electrical characteristics section for more details. cr6 cr9 cr2 cr3 cr4 cr5 cr8 cr7 f osc mccsr sms mco mco f cpu f cpu to cpu and peripherals (1ms timebase @ 8 mhz f osc ) /32 divider f osc f osc /32 f osc f ltimer 1 0 lite timer 2 counter 8-bit at timer 2 12-bit clkin osc2 clkin tunable oscillator rc /2 divider option bits clksel[1:0] osc 1-16 mhz clkin clkin /osc1 osc /2 divider osc/2 clkin/2 clkin/2 option bits clksel[1:0] cr1 cr0 or 32khz ckcntcsr rc/awu clock controller f cpu awu rc osc 8 mhz 2 mhz 1 mhz 4 mhz prescaler 8 mhz (f rc ) rc osc 500 khz ck2 ck1 ck0 pscr rccrh rccrl
st7foxf1, ST7FOXK1, st7foxk2 supply, reset and clock management 39/226 6.2.1 external clock source in this external clock mode, a clock signal (s quare, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. note: when the multi-oscilla tor is not used osci1 and osci2 mu st be tied to ground, and pb1 is selected by default as the external clock. 6.2.2 crystal/cer amic oscillators in this mode, with a self -controlled gain feature, oscillator of any frequency fr om 1 to 16 mhz can be placed on osc1 and osc2 pins. this family of oscillators has the advantage of producing a very accurate rate on the main clock of the st7. in this mode of the multi- oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. the loading capacitance values must be adjust ed according to the selected oscillator. these oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. 6.2.3 internal rc oscillator in this mode, the tunable rc oscillator is used as main clock source. the two oscillator pins have to be tied to ground. the calibration is done th rough the rccrh[7:0] and rccrl[6:5] registers. table 8. st7 clock sources hardware configuration external clock osc1 osc2 external st7 source
supply, reset and clock management st7foxf1, ST7FOXK1, st7foxk2 40/226 6.3 reset sequence manager (rsm) 6.3.1 introduction the reset sequence manager includes three reset sources as shown in figure 14 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset note: a reset can also be triggered following the detection of an illegal op code or prebyte code. refer to section 11.2.1 on page 184 for further details. these sources act on the reset pin and it is always kept low during the delay phase. the reset service routine vector is fixed at addresses fffeh-ffffh in the st7 memory mapping. the basic reset sequence consists of 3 phases as shown in figure 13 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (see ta bl e 1 3 ) caution: when the st7 is unprogrammed or fully erased, the flash is blank and the reset vector is not programmed. for this reason, it is recommended to keep the reset pin in low state until programming mode is entered, in order to avoid unwanted behavior. the 256 or 4096 cpu clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte. the reset vector fetch phase duration is 2 clock cycles. crystal/ceramic resonators internal rc oscillator table 8. st7 clock sources hardware configuration osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7
st7foxf1, ST7FOXK1, st7foxk2 supply, reset and clock management 41/226 figure 13. reset sequence phases table 9. cpu clock delay during reset sequence clock source cpu clock cycle delay internal rc 8 mhz oscillator 4096 internal rc 32 khz oscillator 256 external clock (connected to clkin/pb1 pin) 4096 external crystal/ceramic oscillator (connected to osc1/osc2 pins) 4096 external crystal/ceramic 1-16 mhz oscillator 4096 external crystal/ceramic 32 khz oscillator 256 reset active phase internal reset 256 or 4096 clock cycles fetch vector
supply, reset and clock management st7foxf1, ST7FOXK1, st7foxk2 42/226 6.3.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in accordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristic section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 15: reset sequences ). this detection is asynchronous and therefore the mcu can enter reset state even in halt mode. the reset pin is an asynchronous sign al which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. figure 14. reset block diagram 1. see section 11.2.1: illegal opcode reset on page 184 for more details on illegal opcode reset conditions. 6.3.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specif ied for the selected f osc frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc network connected to the reset pin. 6.3.4 internal low voltage detector (lvd) reset two different reset sequences caused by the internal lvd circuitry can be distinguished: power-on reset voltage drop reset the device reset pin acts as an output that is pulled low when v dd is lower than v it+ (rising edge) or v dd lower than v it- (falling edge) as shown in figure 15. the lvd filters spikes on v dd larger than t g(vdd) to avoid parasitic resets. reset r on v dd internal reset pulse generator filter lvd reset ___ watchdog reset ___ illegal opcode reset 1) ___
st7foxf1, ST7FOXK1, st7foxk2 supply, reset and clock management 43/226 6.3.5 internal watchdog reset the reset sequence generated by an internal watchdog counter overflow is shown in figure 15: reset sequences starting from the watchdog co unter underflow, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . figure 15. reset sequences t w(rstl)out run run watchdog reset internal reset (256 or 4096 t cpu ) vector fetch active phase v dd run reset pin external watchdog active phase v it+(lvd) v it-(lvd) t h(rstl)in run watchdog underflow reset reset source external reset lvd reset active phase
supply, reset and clock management st7foxf1, ST7FOXK1, st7foxk2 44/226 6.4 system integrity management (si) the system integrity management block contains the low voltage detector (lvd). note: a reset can also be triggered following the detection of an illegal opcode or prebyte code. refer to section 11.2.1 on page 184 for further details. 6.4.1 low voltage detector (lvd) the low voltage detector function (lvd) generates a static reset when the v dd supply voltage is below a v it-(lvd) reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it-(lvd) reference value for a voltage drop is lower than the v it+(lvd) reference value for power-on in order to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: v it+(lvd) when v dd is rising v it-(lvd) when v dd is falling the lvd function is illustrated in figure 16 . the voltage threshold can be enabled/disabled by option byte. see section 13.1 on page 211 . provided the minimum v dd value (guaranteed for the osc illator frequency) is above v it-(lvd) , the mcu can only be in two modes: under full software control in static safe reset in these conditions, secure operation is always ensured for the application without the need for external reset hardware. during a low voltage de tector rese t, the reset pin is held low, thus permitting the mcu to reset other devices. note: use of lvd with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull v dd down to 0 v to ensure optimum restart conditions. refer to circuit example in figure 89 on page 207 and note 4. the lvd is an optional function which can be selected by option byte. see section 13.1 on page 211 . it allows the device to be used wit hout any external reset circuitry. if the lvd is disabled, an external circuitry must be used to ensure a proper power-on reset. it is recommended to make sure that the v dd supply voltage rises monotonously when the device is exiting from reset, to ensure the application functions properly. caution: if an lvd reset occurs after a watchdog reset has occurred, the lvd w ill take priority and will clear the watchdog flag.
st7foxf1, ST7FOXK1, st7foxk2 supply, reset and clock management 45/226 figure 16. low voltage detector vs reset figure 17. reset and supply management block diagram v dd v it+(lvd) reset v it-(lvd) v hys low voltage detector (lvd) reset v ss v dd reset sequence manager (rsm) system integrity management watchdog timer (wdg) status flag cr0 cr1 lvdrf 0 wdgf 0 00 rccrl
supply, reset and clock management st7foxf1, ST7FOXK1, st7foxk2 46/226 6.5 register description 6.5.1 rc calibration control/ status register (rcc_csr) reset value: 0000 0000 (00h) bits 7:2 = reserved, forced by hardware to 0 0: read mode 1: write mode bit 1 = rcclat latch access transfer bit: this bit is set by software. it is cleared by hardware at the end of the programming cycle. it can only be cleared by software if the rccpgm bit is cleared bit 0 = rccpgm programming control and status bit this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware. 0: programming finished or not yet started 1: programming cycle is in progress note: if the rccpgm bit is cleared during the prog ramming cycle, the memory data is not guaranteed. 6.5.2 main clock control/ status register (mccsr) reset value: 0000 0000 (00h) bits 7:2 = reserved, must be kept cleared. bit 1 = mco main clock out enable bit this bit is read/write by software and cleared by hardware after a reset. this bit allows to enable the mco output clock. 0: mco clock disabled, i/o port free for general purpose i/o. 1: mco clock enabled. bit 0 = sms slow mode selection bit this bit is read/write by software and cleared by hardware after a reset. this bit selects the input clock f osc or f osc /32. 0: normal mode (f cpu = f osc 1: slow mode (f cpu = f osc /32) 7 0 000000 rcclat rccpgm read/write 7 0 000000mcosms read/write
st7foxf1, ST7FOXK1, st7foxk2 supply, reset and clock management 47/226 6.5.3 rc control register high (rccrh) reset value: 1111 1111 (ffh) bits 7:0 = cr[9:2] rc oscillator frequency adjustment bits these bits must be written immediately af ter reset to adjust the rc oscillator frequency. the application can store the correct value for each voltage range in flash memory and write it to this register at start-up. 00h = maximum available frequency ffh = lowest available frequency these bits are used with the cr[1:0] bits in the rccrl register. refer to chapter 6.5.4 . note: to tune the oscillator, write a series of different values in the register un til the correct frequency is reached. the fastest method is to use a dichotomy starting with 80h. 7 0 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 read/write
supply, reset and clock management st7foxf1, ST7FOXK1, st7foxk2 48/226 6.5.4 rc control register low (rccrl) reset value: 011x 0x00 (xxh) bit 7 = reserved, must be kept cleared bits 6:5 = cr[1:0] rc oscillator frequency adjustment bits these bits, as well as cr[9:2] bits in the rccrh register must be written immediately after reset to adjust the rc oscillator frequency. refer to section 6.1.1: internal rc oscillator on page 34 . bit 4 = wdgrf watchdog reset flag this bit indicates that the last reset was generated by the watchdog peripheral. it is set by hardware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). the wdgrf and the lvdrf flags areis used to select the reset source (see table 10: reset source selection on page 48 ). bit 3 = reserved, must be kept cleared bit 2 = lvdrf lvd reset flag this bit indicates that the last reset was generated by the lvd block. it is set by hardware (lvd reset) and cleared by software (by reading). when the lvd is disabled by option byte, the lvdrf bit value is undefined. the lvdrf flag is not cleared when another reset type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the original failure. in this case, a watchdog reset can be detected by software while an external reset can not. bits 1:0 = reserved, must be kept cleared 7 0 0 cr1 cr0 wdgrf 0 lvdrf 0 0 read/write table 10. reset source selection reset source lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lv d 1 x
st7foxf1, ST7FOXK1, st7foxk2 supply, reset and clock management 49/226 6.5.5 prescaler register (pscr) reset value: 0000 0000 (00h) for st7foxf1 and ST7FOXK1 reset value: 0000 0011 (03h) for st7foxk2 bits 7:5 = ck[2:0] internal rc prescaler selection these bits are set by software and cleared by hardware after a reset. these bits select the prescaler of the internal rc oscillator. see ta b l e 1 1 . if the internal rc is used with a supply operating range below 3.3 v, a division ratio of at least 2 must be enabled in the rc prescaler. bits 4:2 = reserved, must be cleared. bits 1:0 = must be set. caution: for st7foxf1 and ST7FOXK1 devices, prsc[1:0] bits must be forced to 1 by software in order to reduce current consumption. 6.5.6 clock controller control /status register (ckcntcsr) reset value: 0000 1001 (09h) bits 7:4 = reserved, must be kept cleared. bit 3 = awu_flag awu selection bit this bit is set and cleared by hardware. 0: no switch from awu to rc requested 1: awu clock activated and temporization completed 7 0 ck2 ck1 ck0 0 0 0 0 or 1 0 or 1 read/write table 11. internal rc prescaler selection bits ck2 ck1 ck0 f osc 001 f rc/2 010 f rc/4 011 f rc/8 100 f rc/16 others f rc 7 0 0 0 0 0 awu_flag rc_flag 0 rc/awu read/write
supply, reset and clock management st7foxf1, ST7FOXK1, st7foxk2 50/226 bit 2 = rc_flag rc selection bit this bit is set and cleared by hardware. 0: no switch from rc to awu requested 1: rc clock activated and temporization completed bit 1 = reserved, must be kept cleared. bit 0 = rc/awu rc/awu selection bit 0: rc enabled 1: awu enabled (default value) table 12. clock register mapping and reset values addre ss (hex.) register label 765 4 3 2 1 0 0035h rcc_csr - 0 - 0 - 0 - 0 - 0 - 0 rcclat 0 rccpgm 0 003ah mccsr reset value - 0 - 0 - 0 - 0 - 0 - 0 mco 0 sms 0 003bh rccrh reset value cr9 1 cr8 1 cr7 1 cr6 1 cr5 1 cr4 1 cr3 1 cr2 1 003ch rccrl reset value - 0 cr1 1 cr0 1 wdgrf 0 - 0 lvdrf x - 0 - 0 003dh pscr reset value ck2 0 ck1 0 ck0 0 - 0 - 0 - 0 - 0 or 1 - 0 or 1 0051h ckcntcsr reset value - 0 - 0 - 0 - 0 awu_ flag 1 rc_fla g 0 - 0 rc/awu 1
st7foxf1, ST7FOXK1, st7foxk2 interrupts 51/226 7 interrupts 7.1 introduction the st7 enhanced interrupt management provides the following features: hardware interrupts software interrupt (trap) nested or concurrent interrupt management with flexible interrupt priority and level management: ? up to 4 software programmable nesting levels ? 13 interrupt vectors fixed by hardware ? 2 non maskable events: reset, trap this interrupt management is based on: bit 5 and bit 3 of the cpu cc register (i1:0), interrupt software priority registers (isprx), fixed interrupt vector addresses located at the high addresses of the memory mapping (ffe0h to ffffh) sorted by hardware priority order. this enhanced in terrupt controller guarant ees full upward compatib ility with the standard (not nested) st7 interrupt controller. 7.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see ta bl e 1 3 ). the processing flow is shown in figure 18 . when an interrupt request has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to interrupt mapping table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, th e i1 and i0 bits will be restored from the stack and the program in the pr evious level will resume.
interrupts st7foxf1, ST7FOXK1, st7foxk2 52/226 figure 18. interrupt processing flowchart table 13. interrupt software priority levels interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 level 3 (= interrupt disable) 1 1 ?iret? restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset tli pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt
st7foxf1, ST7FOXK1, st7foxk2 interrupts 53/226 7.2.1 servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. figure 19 describes this decision process. figure 19. priority decision process when an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. note: 1 the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. 2 reset and trap can be considered as having the highest software priority in the decision process. 7.2.2 interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, trap) and the maskable type (e xternal or from in ternal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 18 ). after stacking the pc, x, a and cc registers (except for reset), the corresponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. trap (non maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced according to the flowchart in figure 18 . reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the highest hardware priority. see the reset chapter for more details. pending software different interrupts same highest hardware priority serviced priority highest software priority serviced
interrupts st7foxf1, ST7FOXK1, st7foxk2 54/226 maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if an y of these two conditions is false, the interrupt is latched and thus remains pending. external interrupts external interrupts allow the processo r to exit from halt low power mode. external interrupt sensitivity is software selectable through the external interrupt control register (eicr). external interrupt trigger ed on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ored. peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in table 17: st7foxf1/ST7FOXK1 interrupt mapping . a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note: the clearing sequence resets the internal latch. a pending interrupt (that is, waiting for being serviced) will theref ore be lost if the clea r sequence is executed. 7.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column ?exit from halt? in table 17: st7foxf1/ST7FOXK1 interrupt mapping ). when several pending interrupts are present while exiting halt mode, the first one serviced can only be an interrupt with exit from halt mode capability and it is selected through the same decision process shown in figure 19 . note: if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced.
st7foxf1, ST7FOXK1, st7foxk2 interrupts 55/226 7.4 concurrent and nested management the following figure 20 and figure 21 show two different interrupt management modes. the first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in figure 21 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it5, it4, it3, it2, it1, it0. the software priority is given for each interrupt. caution: a stack overflow may occur without notifying the software of the failure. figure 20. concurrent interrupt management figure 21. nested interrupt management main it5 it3 it2 it0 it2 main it1 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it3 it2 it5 it0 it4 it1 it4 i0 10 priority level used stack = 10 bytes main it2 tli main it0 it3 it2 it5 it0 it4 it1 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes
interrupts st7foxf1, ST7FOXK1, st7foxk2 56/226 7.5 description of interrupt registers 7.5.1 cpu cc register interrupt bits reset value: 111x 1010(xah) bits 5, 3 = i1, i0 software interrupt priority bits these two bits indicate the current interrupt software priority (see ta bl e 1 4 ). these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop instructions (see table 16: dedicated interrupt instruction set ). trap and reset events can interrupt a level 3 program. 7.5.2 interrupt software pr iority registers (isprx) all isprx register bits are read/write except bit 7:4 of ispr3 which are read only. reset value: 1111 1111 (ffh) isprx registers contain the interrupt software priority of each interrupt vector. each interrupt vector (except reset and trap) has corresponding bits in these registers to define its software priority. this correspondence is shown in ta bl e 1 5 . each i1_x and i0_x bit value in the isprx registers has the same meaning as the i1 and i0 bits in the cc register. 7 0 11i1hi0nzc read/write table 14. setting the interrupt software priority interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 level 3 (= interrupt disable*) 1 1 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 111111i1_12i0_12
st7foxf1, ST7FOXK1, st7foxk2 interrupts 57/226 the reset and trap vectors have no software priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. level 0 cannot be written (i1_x = 1, i0_x = 0). in this case, the previously stored value is kept (example: previous = cfh, write = 64h, result = 44h). caution: if the i1_x and i0_x bits are modified while the interrupt x is executed the following behavior has to be considered: if the inte rrupt x is still pending (new inte rrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the interrupt x). table 15. interrupt vector vs isprx bits vector address isprx bits fffbh-fffah i1_0 and i0_0 bits (1) 1. bits in the isprx registers can be read and written but they are not significant in the interrupt process management. fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits table 16. dedicated interrupt instruction set (1) 1. during the execution of an interrupt routine, the ha lt, popcc, rim, sim and wfi instructions change the current software priority up to the next iret instruct ion or one of the previous ly mentioned instructions. instruction new description function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0 = 11 (level 3) i1:0 = 11 jrnm jump if i1:0 <> 11 i1:0 <> 11 pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0
interrupts st7foxf1, ST7FOXK1, st7foxk2 58/226 table 17. st7foxf1/ST7FOXK1 interrupt mapping number source block description register label priority order exit from halt or awufh (1) address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 awu auto wake up interrupt awucsr yes (2) fffah-fffbh 1 reserved - fff8h-fff9h 2 ei0 external interrupt 0 (port a) n/a yes fff6h-fff7 3 ei1 external interrupt 1 (port b) fff4h-fff5h 4 ei2 external interrupt 2 (port c) fff2h-fff3h 5 at t i m e r at timer output compare interrupt at c s r no fff0h-fff1h 6 at timer input capture interrupt no ffeeh-ffefh 7 (3) at timer overflow 1 interrupt no ffech-ffedh 8 at timer overflow 2 interrupt no ffeah-ffebh 9i 2 ci 2 c interrupt n/a no ffe8h-ffe9h 10 (3) lite timer lite timer rtc interrupt lt c s r 2 yes ffe6h-ffe7h 11 lite timer input capture interrupt no ffe4h-ffe5h 12 lite timer rtc2 interrupt no ffe2h-ffe3h 1. for an interrupt, all events do not have the same capability to wake up the mcu from halt, active-halt or auto wake-up from halt modes. refer to the description of interrupt events for more details. 2. this interrupt exits the mcu from auto wake-up from halt mode only. 3. these interrupts exit the m cu from active-halt mode only.
st7foxf1, ST7FOXK1, st7foxk2 interrupts 59/226 table 18. st7foxk2 interrupt mapping number source block description register label priority order exit from halt or awufh (1) address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 awu auto wake up interrupt awucsr yes (2) fffah-fffbh 1 reserved - fff8h-fff9h 2 reserved - fff6h-fff7h 3 reserved - fff4h-fff5h 4 ei0 external interrupt 0 (port a) n/a yes fff2h-fff3h 5 ei1 external interrupt 1 (port b) fff0h-fff1h 6 ei2 external interrupt 2 (port c) ffeeh-ffefh 7 at t i m e r at timer input capture/output compare interrupt at c s r no ffech-ffedh 8 (3) at timer overflow 1 interrupt no ffeah-ffebh 9 at timer overflow 2 interrupt no ffe8h-ffe9h 10 i 2 ci 2 c interrupt i2csr1/ i2csr2 no ffe6h-ffe7h 11 spi spi interrupt spicsr no ffe4h-ffe5h 12 tim16 16-bit timer peripheral interrupt tacsr no ffe2h-ffe3h 13 (3) lite timer lite timer rtc/ic/rtc2 interrupt ltcsr2 yes ffe0h-ffe1h 1. for an interrupt, all events do not have the same capability to wake up the mcu from halt, active-halt or auto-wakeup from halt modes. refer to the description of interrupt events for more details. 2. this interrupt exits the mcu from auto-wakeup from halt mode only. 3. these interrupts exit the m cu from active-halt mode only.
interrupts st7foxf1, ST7FOXK1, st7foxk2 60/226 7.5.3 external interrupt control register (eicr) reset value: 0000 0000 (00h) bits 7:6 = reserved, must be kept cleared. bits 5:4 = is2[1:0] ei2 sensitivity bits these bits define the interrupt sensitivity for ei2 (port c) according to ta b l e 1 9 . bits 3:2 = is1[1:0] ei1 sensitivity bits these bits define the interrupt sensitivity for ei1 (port b) according to ta bl e 1 9 . bits 1:0 = is0[1:0] ei0 sensitivity bits these bits define the interrupt sensitivity for ei0 (port a) according to ta bl e 1 9 . note: 1 these 8 bits can be written only when the i bit in the cc register is set. 2 changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts. refer to section : external interrupt function . 7 0 0 0 is21 is20 is11 is10 is01 is00 read/write table 19. interrupt sensitivity bits isx1 isx0 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge
st7foxf1, ST7FOXK1, st7foxk2 power saving modes 61/226 8 power saving modes 8.1 introduction to give a large measure of flexibility to the ap plication in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 22 ): slow wait (and slow-wait) active halt auto wakeup from halt (awufh) halt after a reset the normal operating mode is selected by default (run mode). this mode drives the device (cpu and embedded periphera ls) by means of a master clock which is based on the main os cillator frequency (f osc ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instructi on whose action depends on the oscillator status. figure 22. power saving mode transitions power consumption wait slow run active halt high low slow wait halt
power saving modes st7foxf1, ST7FOXK1, st7foxk2 62/226 8.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device, to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by the sms bit in the mccsr register which enables or disables slow mode. in this mode, the oscillator fr equency is divided by 32. the cpu and peripherals are clocked at this lower frequency. note: slow-wait mode is activated when entering wa it mode while the device is already in slow mode. figure 23. slow mode clock transition 8.3 wait mode wait mode places the mcu in a low power consumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. du ring wait mode, the i bit of the cc register is cleared, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 24 for a description of the wait mode flowchart. sms f cpu normal run mode request f osc f osc /32 f osc
st7foxf1, ST7FOXK1, st7foxk2 power saving modes 63/226 figure 24. wait mode flowchart 1. before servicing an interrupt, the cc register is pus hed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. 8.4 active-halt and halt modes active-halt and halt modes are the two lowest power consumption modes of the mcu. they are both entered by executing the ?halt? instruction. the decision to enter either in active- halt or halt mode is given by the ltcsr/atcs r register status as shown in the following table: wfi instruction reset interrupt y n n y cpu oscillator peripherals ibit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off 0 on cpu oscillator peripherals ibit on on x 1) on 256 cpu clock cycle delay table 20. enabling/disabling active-halt and halt modes ltcsr tbie bit atcsr ovfie bit atcsrck1 bit atcsrck0 bit meaning 0xx0 active-halt mode disabled 00xx 0111 1xxx active-halt mode enabled x101
power saving modes st7foxf1, ST7FOXK1, st7foxk2 64/226 8.4.1 active-halt mode active-halt mode is the lowest power consumption mode of the mcu with a real-time clock available. it is entered by executing the ?halt? instruction when active halt mode is enabled. the mcu can exit active-halt mode on reception of a lite timer/ at timer interrupt or a reset. when exiting active-halt mode by means of a reset, a 256 cpu cycle delay occurs. after the start up delay, the cpu resumes operation by fetching the reset vector which woke it up (see figure 26 ). when exiting active-halt mode by means of an interrupt, the cpu immediately resumes operation by servicing the inte rrupt vector which woke it up (see figure 26 ). when entering active-halt mode, the i bit in the cc register is cleared to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, only the main oscillato r and the select ed timer counter (lt/at) are running to keep a wakeup time base. all other peripherals are not clocked except those which get their clock supply from another cloc k generator (such as external or auxiliary oscillator). caution: as soon as active-halt is enabled, executing a halt instruction while the watchdog is active does not generate a reset if the wdghalt bit is reset. this means that the device cannot spend more than a defined delay in this power saving mode. figure 25. active-halt timing overview 1. this delay occurs only if the mcu exit s active-halt mode by means of a reset. halt run run 256 cpu cycle delay 1) reset or interrupt halt instruction fetch vector active [active halt enabled]
st7foxf1, ST7FOXK1, st7foxk2 power saving modes 65/226 figure 26. active-halt mode flowchart 1. this delay occurs only if the mcu exit s active-halt mode by means of a reset. 2. peripherals clocked with an external clock source can still be active. 3. only the lite timer rtc and at timer inte rrupts can exit the mcu from active-halt mode. 4. before servicing an interrupt, the cc register is pus hed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. 8.4.2 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the halt instruction when active halt mode is disabled. the mcu can exit halt mode on reception of either a specific interrupt (see ta bl e 1 7 : st7foxf1/ST7FOXK1 interrupt mapping ) or a reset. when exiting halt mode by means of a reset or an interrupt, the ma in oscillator is immediately tu rned on and the 256 cpu cycle delay is used to stabilize it. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 28 ). when entering halt mode, the i bit in the cc register is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes immediately. in halt mode, the main oscillator is turned off causing all intern al processing to be stopped, including the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). the compatibility of watc hdog operation with halt mode is configured by the ?wdghalt? option bit of the option byte. the halt instruction when executed while the watchdog system is enabled, can generate a watchdog reset (see section 13.1: option bytes for more details). halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit on off 0 off fetch reset vector or service interrupt cpu oscillator peripherals 2) ibit on off x 4) on cpu oscillator peripherals ibits on on x 4) on 256 cpu clock cycle delay (active halt enabled)
power saving modes st7foxf1, ST7FOXK1, st7foxk2 66/226 figure 27. halt timing overview 1. a reset pulse of at least 42 s must be applied when exiting from halt mode. figure 28. halt mode flowchart 1. wdghalt is an option bit. see option byte section for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 17: st7foxf1/ST7FOXK1 interrupt mapping for more details. 4. before servicing an interrupt, the cc register is pus hed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. 5. the cpu clock must be switched to 1 mhz ( rc/8) or awu rc before entering halt mode. halt run run 256 cpu cycle delay reset or interrupt halt instruction fetch vector [ active halt disabled ] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off x 4) on cpu oscillator peripherals ibits on on x 4) on 256 cpu clock cycle delay 5) watchdog enable disable wdghalt 1) 0 watchdog reset 1 (active halt disabled)
st7foxf1, ST7FOXK1, st7foxk2 power saving modes 67/226 halt mode recommendations make sure that an external event is available to wake up the microcontroller from halt mode. when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. for the same reason, reinitialize the level sens itiveness of each external interrupt as a precautionary measure. the opcode for the halt instruction is 0x8e . to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memory. for example, avoid defining a constant in rom with the value 0x8e. as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt). 8.5 auto-wakeup from halt mode auto wakeup from halt (awufh) mode is similar to halt mode with the addition of a specific internal rc oscillator for wakeup (auto-wakeup from halt oscilla tor) which replaces the main clock which was active before entering halt mode. compared to active-halt mode, awufh has lower power consumption (the main clock is not kept running), but there is no accurate real-time clock available. it is entered by executing the halt inst ruction when the awuen bit in the awucsr register has been set. figure 29. awufh mode block diagram awu rc awufh f awu_rc awufh (ei0 source) oscillator prescaler/1 .. 255 interrupt /64 divider to 8-bit timer input capture
power saving modes st7foxf1, ST7FOXK1, st7foxk2 68/226 as soon as halt mode is entered, and if the awuen bit has been set in the awucsr register, the awu rc oscillator provides a clock signal (f awu_rc ). its frequency is divided by a fixed divider and a programmable prescaler controlled by the awupr register. the output of this prescaler provides the delay time. when the delay has elapsed, the following actions are performed: the awuf flag is set by hardware, an interrupt wakes-up the mcu from halt mode, the main oscillator is immediately turned on and the 256 cpu cycle delay is used to stabilize it. after this start-up delay, the cpu resumes ope ration by servicing the awufh interrupt. the awu flag and its associated interrupt are cleared by software reading the awucsr register. to compensate for any frequency dispersion of the awu rc oscillator, it can be calibrated by measuring the clock frequency f awu_rc and then calculating the right prescaler value. measurement mode is enabled by setting the awum bit in the awucsr register in run mode. this connects f awu_rc to the input capture of the 8-bit lite timer, allowing the f awu_rc to be measured using the main oscillator cloc k as a reference timebase. similarities with halt mode the following awufh mode behavior is the same as normal halt mode: the mcu can exit awufh mode by means of any interrupt with exit from halt capability or a reset (see section 8.4: active-halt and halt modes ). when entering awufh mode, the i bit in the cc register is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in awufh mode, the main oscilla tor is turned off causing a ll internal processing to be stopped, including the operation of the on-chip peripherals. none of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the awu oscillator). the compatibility of watchdog operation wi th awufh mode is configured by the wdghalt option bit in the option byte. depending on this setting, the halt instruction when executed while the watchdog system is enabled, can generate a watchdog reset. figure 30. awuf halt timing diagram awufh interrupt f cpu run mode halt mode 256 t cpu run mode f awu_rc clear by software t awu
st7foxf1, ST7FOXK1, st7foxk2 power saving modes 69/226 figure 31. awufh mode flowchart 1. wdghalt is an option bit. see option byte section for more details. 2. peripheral clocked with an external clock source can still be active. 3. only an awufh interrupt and some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 17: st7foxf1/ST7FOXK1 interrupt mapping for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and recovered when the cc register is popped. reset interrupt 3) y n n y cpu main osc peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu main osc peripherals i[1:0] bits on off xx 4) on cpu main osc peripherals i[1:0] bits on on xx 4) on 256 cpu clock delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle awu rc osc on awu rc osc off awu rc osc off halt instruction (active-halt disabled) (awucsr.awuen=1)
power saving modes st7foxf1, ST7FOXK1, st7foxk2 70/226 8.5.1 register description 8.5.2 awufh control/st atus register (awucsr) reset value: 0000 0000 (00h) bits 7:3 = reserved bit 2 = awuf auto wakeup flag this bit is set by hardware when the awu module generates an interrupt and cleared by software on reading awucsr. writing to this bit does not change its value. 0: no awu interrupt occurred 1: awu interrupt occurred bit 1 = awum auto wakeup measurement bit this bit enables the awu rc oscillator and co nnects its output to the input capture of the 8-bit lite timer. this allows the timer to be used to measur e the awu rc oscillator dispersion and then compensate this dispersion by providing the right value in the awupre register. 0: measurement disabled 1: measurement enabled bit 0 = awuen auto wakeup from halt enabled bit this bit enables the auto wakeup from halt feature: once halt mode is entered, the awufh wakes up the microcontroller after a time delay dependent on the awu prescaler value. it is se t and cleared by software. 0: awufh (auto wakeup from halt) mode disabled 1: awufh (auto wakeup from halt) mode enabled note: whatever the clock source, this bit should be set to enable the awufh mode once the halt instruction has been executed. 7 0 00000 awu f awum awuen read/write
st7foxf1, ST7FOXK1, st7foxk2 power saving modes 71/226 8.5.3 awufh prescaler register (awupr) reset value: 1111 1111 (ffh) bits 7:0= awupr[7:0] auto wakeup prescaler these 8 bits define the awupr dividing factor (see ta b l e 2 1 ). in awu mode, the time during which the mcu stays in halt mode, t awu , is given by the equation below. see also figure 30 on page 68 . the awupr prescaler register can be programmed to modify the time during which the mcu stays in halt mode before waking up automatically. note: if 00h is written to awupr, the awupr remains unchanged. 7 0 awupr7 awupr6 awupr5 awupr4 awupr3 awupr2 awupr1 awupr0 read/write table 21. configuring the dividing factor awupr[7:0 ] dividing factor 00h forbidden 01h 1 ... ... feh 254 ffh 255 t awu 64 awupr 1 f awurc -------------------- t rcstrt + = table 22. awu register mapping and reset values address (hex.) register label 76543210 0048h awucsr reset value 00000awufawumawuen 0049h awupr reset value awupr7 1 awupr6 1 awupr5 1 awupr4 1 awupr3 1 awupr2 1 awupr1 1 awupr0 1
i/o ports st7foxf1, ST7FOXK1, st7foxk2 72/226 9 i/o ports 9.1 introduction the i/o ports allow data transfer. an i/o port can contain up to 8 pins. each pin can be programmed independently either as a digital input or digital output. in addition, specific pins may have several other functions. these functions can include external interrupt, alternate signal input/output for on-chip peripherals or analog input. 9.2 functional description a data register (dr) and a da ta direction register (ddr) are always associated with each port. the option register (or), which allows input/output options, may or may not be implemented. the following description takes into account the or register. refer to the port configuration table for devi ce specific information. an i/o pin is programmed using the corresponding bits in the ddr, dr and or registers: bit x corresponding to pin x of the port. figure 32 shows the generic i/o block diagram. 9.2.1 input modes clearing the ddrx bit selects input mode. in this mode, reading its dr bit returns the digital value from that i/o pin. if an or bit is available, different input modes can be configured by software: floating or pull- up. refer to i/o port implementation section for configuration. note: 1 writing to the dr modifies the latch value but does not change the state of the input pin. 2 do not use read/modify/write instructions (bset/bres) to modify the dr register. external interrupt function depending on the device, setting the orx bit while in input mode can configure an i/o as an input with interrupt. in this configuration, a signal edge or level input on the i/o generates an interrupt request via the corresponding interrupt vector (eix). falling or rising edge sensitivity is programmed independently for each interrupt vector. the external interrupt control register (eicr) or the miscellaneous register controls this sensitivity, depending on the device. each external interrupt vector is linked to a dedicated group of i/o port pins (see pinout description and interrupt section). if several i/o interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. for this reason if one of the interrupt pins is tied low, it may mask the others. external interrupts are hardware interrupts. fetching the corresponding interrupt vector automatically clears the request latch. changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts.
st7foxf1, ST7FOXK1, st7foxk2 i/o ports 73/226 spurious interrupts when enabling/disabling an external interrupt by setting/resetting the related or register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. this is due to the edge dete ctor input which is s witched to '1' when the external interrupt is disabled by the or register. to avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the or register bit and configuring the appropriate sensitivity again. caution: in case a pin level change occurs during these operations (asynchronous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge. this corresponds to the following steps: a) set the interrupt mask with the sim instruction (in cases where a pin level change could occur) b) select rising edge c) enable the external interrupt through the or register d) select the desired sensitivity if different from rising edge e) reset the interrupt mask with the rim instruction (in cases where a pin level change could occur) 2. to disable an external interrupt: a) set the interrupt mask with the sim inst ruction sim (in cases where a pin level change could occur) b) select falling edge c) disable the external interrupt through the or register d) select rising edge e) reset the interrupt mask with the rim instruction (in cases where a pin level change could occur) 9.2.2 output modes setting the ddrx bit selects output mode. writing to the dr bits applies a digital value to the i/o through the latch. reading the dr bits returns the previously stored value. if an or bit is available, different output modes can be selected by software: push-pull or open-drain. refer to i/o port implementation section for configuration. table 23. dr value and output pin status dr push-pull open-drain 0v ol v ol 1v oh floating
i/o ports st7foxf1, ST7FOXK1, st7foxk2 74/226 9.2.3 alternate functions many st7s i/os have one or more alternate functions. these may include output signals from, or input signals to, on-chip peripherals. ta bl e 2 and ta b l e 3 describe which peripheral signals can be input/output to which ports. a signal coming from an on-chip peripheral can be output on an i/o. to do this, enable the on-chip peripheral as an output (enable bit in the peripheral?s control register). the peripheral configures the i/o as an output and takes priority over standard i/o programming. the i/o?s state is readable by addressing the corresponding i/o data register. configuring an i/o as floating enables alternate function input. it is not recommended to configure an i/o as pull-up as this will increase current consumpt ion. before using an i/o as an alternate input, configure it without interrupt. otherwise spurious interrupts can occur. configure an i/o as input floating for an on-chip peripheral signal which can be input and output. caution: i/os which can be configured as both an analog and digital alternate function need special attention. the user must control the peripherals so that the signals do not arrive at the same time on the same pin. if an external clock is used, only the clock alternate function should be employed on that i/o pin and not the other alternate function. figure 32. i/o port general block diagram dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external request (ei x ) interrupt sensitivity selection cmos schmitt trigger register access bit from on-chip periphera l to on-chip peripheral note : refer to the port configuration table for device specific information. combinational logic
st7foxf1, ST7FOXK1, st7foxk2 i/o ports 75/226 table 24. i/o port mode options (1) 1. off means implemented not activat ed, on means implemented and activated. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with interrupt on output push-pull off on open drain (logic level) off table 25. st7foxf1/ST7FOXK1/st7foxk2 i/o port configuration hardware configuration input (1) 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read th e alternate function output status. open-drain output (2) 2. when the i/o port is in output configuration and t he associated alternate func tion is enabled as an input, the alternate function reads the pin stat us given by the dr register content. push-pull output (2) condition pad external int errupt polarity data bus interrupt dr register access w r from other pins source (ei x ) selection dr register alternate input analog input to on-chip peripheral combinational logic pad data bus dr dr register access r/w register pad data bus dr dr register access r/w alternate alternate enable output register bit from on-chip periphera l
i/o ports st7foxf1, ST7FOXK1, st7foxk2 76/226 9.2.4 analog alternate function configure the i/o as floating input to use an adc input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the adc input. analog recommendations do not change the voltage level or loading on any i/o while conversion is in progress. do not have clocking pins located close to a selected analog pin. caution: the analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 i/o port implementation the hardware implementation on each i/o port depends on the settings in the ddr and or registers and specific i/o port features such as adc input or open drain. switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommend ed safe transitions are illustrated in figure 33 . other transitions are potentially risky and s hould be avoided, since they may present unwanted side-effects such as spurious interrupt generation. figure 33. interrupt i/o port state transitions 9.4 unused i/o pins unused i/o pins must be connected to fixed voltage levels. refer to section 12.9: i/o port pin characteristics . 9.5 low power modes s 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or table 26. effect of low power modes on i/o ports mode description wait no effect on i/o ports. external interrup ts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode.
st7foxf1, ST7FOXK1, st7foxk2 i/o ports 77/226 9.6 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and if the i bit in the cc register is cleared (rim instruction). see application notes an1045 software implementation of i 2 c bus master, and an1048 - software lcd driver 9.7 device-specific i/o port configuration the i/o port register configurations are summarized in section 9.7.1: standard ports and section 9.7.2: other ports . 9.7.1 standard ports 9.7.2 other ports table 27. description of interrupt events interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx ye s ye s table 28. pa5:0, pb7:0, pc7:4 and pc2:0 pins mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 table 29. pa7:6 pins mode ddr or floating input 0 0 interrupt input 0 1 open drain output 1 0 push-pull output 1 1
i/o ports st7foxf1, ST7FOXK1, st7foxk2 78/226 m table 30. pc3 pin mode ddr or floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 table 31. port configuration port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa5:0 floating pull-up interrupt open drain push-pull pa7:6 floating interrupt true open drain port b pb7:0 floating pull-up interrupt open drain push-pull port c pc7:4, pc2:0 floating pull-up interrupt open drain push-pull pc3 floating pull-up open drain push-pull table 32. i/o port register mapping and reset values address (hex.) register label 76543210 0000h pa d r reset value msb 0000000 lsb 0 0001h paddr reset value msb 0000000 lsb 0 0002h pao r reset value msb 0000000 lsb 0 0003h pbdr reset value msb 0000000 lsb 0 0004h pbddr reset value msb 0000000 lsb 0 0005h pbor reset value msb 0000000 lsb 0 0006h pcdr reset value msb 0000000 lsb 0 0007h pcddr reset value msb 0000000 lsb 0 0008h pcor reset value msb 0000100 lsb 0
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 79/226 10 on-chip peripherals 10.1 watchdog timer (wdg) 10.1.1 introduction the watchdog timer is used to detect the oc currence of a software fault, usually generated by external interference or by unforeseen lo gical conditions, which causes the application program to abandon its normal sequence. the watchdog circuit generates an mcu reset on expiry of a programmed time period, unless the program refreshes the counter?s contents before the t6 bit becomes cleared. 10.1.2 main features programmable free-running downcounter (64 increments of 16000 cpu cycles) programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte 10.1.3 functional description the counter value stored in the cr register (bits t[6:0]), is decremented every 16000 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 beco mes cleared), it initiates a reset cycle pulling low the reset pin for typically 30s. figure 34. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 16000 t1 t2 t3 t4 t5
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 80/226 the application program must write in the cr register at regular intervals during normal operation to prevent an mcu reset. this downcounter is free-running: it counts down even if the watchdog is disabled. the value to be stored in the cr register must be between ffh and c0h (see table 33: watchdog timing ): the wdga bit is set (watchdog enabled) the t6 bit is set to prevent generating an immediate reset the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. 10.1.4 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the option byte description in section 13 on page 211 . using halt mode with the wdg (wdghalt option) if halt mode with watchdog is enabled by option byte (no watchdog reset on halt instruction), it is recommended before executing the halt instruction to refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcontroller. same behavior in active-halt mode. 10.1.5 interrupts none. table 33. watchdog timing (1)(2) 1. the timing variation shown in table 33 is due to the unknown status of the prescaler when writing to the cr register. 2. the number of cpu clock cycles applied during the re set phase (256 or 4096) must be taken into account in addition to these timings. f cpu = 8 mhz wdg counter code min [ms] max [ms] c0h 1 2 ffh 127 128
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 81/226 10.1.6 register description control register (wdgcr) reset value: 0111 1111 (7fh) bit 7 = wdga activation bit this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watchdog option is enabled by option byte. bits 6:0 = t[6:0] 7-bit timer (msb to lsb) these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). 7 0 wdga t6 t5 t4 t3 t2 t1 t0 read/write table 34. watchdog timer register mapping and reset values address (hex.) register label 76543210 0033h wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 82/226 10.2 dual 12-bit autoreload timer 10.2.1 introduction the 12-bit autoreload timer can be used for general-purpose timing functions. it is based on one or two free-running 12-bit upcounters with an input capture register and four pwm output channels. there are 7 external pins: four pwm outputs atic/ltic pins for the input capture function break pins for forcing a break condition on the pwm outputs 10.2.2 main features single timer or dual timer mode with two 12-bit upcounters (cntr1/cntr2) and two 12-bit autoreload registers (atr1/atr2) maskable overflow interrupts pwm mode ? generation of four independent pwmx signals ? dead time generation for half bridge driving mode with programmable dead time ? frequency 2 khz - 4 mhz (@ 8 mhz f cpu ) ? programmable duty-cycles ? polarity control ? programmable output modes output compare mode input capture mode ? 12-bit input capture register (aticr) ? triggered by risi ng and falling edges ? maskable ic interrupt ? long range input capture internal/external break control flexible clock control one pulse mode on pwm2/3 force update
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 83/226 figure 35. single ti mer mode (encntr2=0) figure 36. dual timer mode (encntr2=1) pwm0 pwm1 pwm2 pwm3 dead time generator pwm3 duty cycle generator 12-bit input capture pwm2 duty cycle generator pwm1 duty cycle generator pwm0 duty cycle generator 12-bit autoreload register 1 12-bit upcounter 1 output compare cmp interrupt ovf1 interrupt edge detection circuit oe0 oe1 oe2 oe3 dte bit bpen bit break function atic clock control f cpu lite timer 1 ms from off pwm0 pwm1 pwm2 pwm3 dead time generator pwm3 duty cycle generator 12-bit input capture 12-bit autoreload register 2 12-bit upcounter 2 pwm2 duty cycle generator pwm1 duty cycle generator pwm0 duty cycle generator 12-bit autoreload register 1 12-bit upcounter 1 output compare cmp interrupt ovf1 interrupt ovf2 interrupt edge detection circuit oe0 oe1 oe2 oe3 atic dte bit bpen bit break function ltic op_en bit clock control f cpu one pulse mode output compare cmp interrupt lite timer 1 ms from off
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 84/226 10.2.3 functional description pwm mode this mode allows up to four pulse width modulated signals to be generated on the pwmx output pins. pwm frequency the four pwm signals can have the same frequency (f pwm ) or can have two different frequencies. this is selected by the encntr2 bit which enables single timer or dual timer mode (see figure 35 and figure 36 ). the frequency is controlled by the counter period and the atr register value. in dual timer mode, pwm2 and pwm3 can be generated with a different frequency controlled by cntr2 and atr2. following the above formula, if f counter equals 4 mhz , the maximum value of f pwm is 2 mhz (atr register value = 4094), and the minimum value is 1 khz (atr register value = 0). the maximum value of atr is 4094 because it must be lower than the dc4r value which must be 4095 in this case. duty cycle the duty cycle is selected by programmin g the dcrx registers. these ar e preload registers. the dcrx values are transferred in active duty cycle registers after an overflow event if the corresponding transfer bit (tranx bit) is set. the tran1 bit controls the pwmx outputs driven by counter 1 and the tran2 bit controls the pwmx outputs driven by counter 2. pwm generation and output compare are done by comparing these active dcrx values with the counter. the maximum available resoluti on for the pwmx duty cycle is: where atr is equal to 0. with this maximum resolution, 0% and 100% duty cycle can be obtained by changing the polarity. at reset, the counter starts counting from 0. when a upcounter overflow occurs (ovf event), the preloaded duty cycle values are transferred to the active duty cycle regist ers and the pwmx signals are set to a high level. when the upcounter matches the active dcrx value the pwmx signals are set to a low level. to obtain a signal on a pwmx pin, the contents of the corresponding active dcrx register must be greater than the contents of the atr register. the maximum value of atr is 4094 because it must be lower than the dcr value which must be 4095 in this case. polarity inversion the polarity bits can be used to invert any of the four output signals. the inversion is synchronized with the counter overflow if the corresponding transfer bit in the atcsr2 register is set (reset value). see figure 37 . f pwm f counter 4096 atr ? () ? = resolution 1 4096 atr ? () ? =
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 85/226 figure 37. pwm polarity inversion the data flip flop (dff) applies the polarity inversion when triggered by the counter overflow input. output control the pwmx output signals can be enabled or disabled using the oex bits in the pwmcr register. figure 38. pwm function pwmx pwmx pin counter overflow opx pwmxcsr register inverter dff tranx atcsr2 register duty cycle register auto-reload register pwmx output t 4095 000 with oe=1 and opx=0 (atr) (dcrx) with oe=1 and opx=1 counter
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 86/226 figure 39. pwm signal from 0% to 100% duty cycle dead time generation a dead time can be inserted between pwm0 and pwm1 using the dtgr register. this is required for half-bridge driving where pwm signals must not be overlapped. the non- overlapping pwm0/pwm1 signals are generated through a programmable dead time by setting the dte bit. dtgr[7:0] is buffered inside so as to avoid deforming the current pwm cycle. the dtgr effect will take place only after an overflow. note: 1 dead time is generated only when dte=1 and dt[6:0] 0 . if dte is set and dt[6:0]=0, pwm output signals will be at their reset state. 2 half bridge driving is possible only if polarities of pwm0 and pwm1 are not inverted, i.e. if op0 and op1 are not set. if polarity is in verted, overlapping pwm0/pwm1 signals will be generated. 3 dead time generation does not work at 1msec timebase. counter pwmx output t with mod00=1 and opx=0 ffdh ffeh fffh ffdh ffeh fffh ffdh ffeh dcrx=000h dcrx=ffdh dcrx=ffeh dcrx=000h atr= ffdh f counter pwmx output with mod00=1 and opx=1 dead time dt 6:0 [] tcounter1 =
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 87/226 figure 40. dead time generation in the above example, when the dte bit is set: pwm goes low at dcr0 match and goes high at atr1+tdt pwm1 goes high at dcr0+tdt and goes low at atr match. with this programmable delay (tdt), the pwm0 and pwm1 signals which are generated are not overlapped. break function the break function can be used to perform an emergency shutdown of the application being driven by the pwm signals. the break functi on is activated by the external break pin. this can be selected by using the brsel bit in breakcr register. in order to use the break func tion it must be previously enabled by software setting the bpen bit in the breakcr register. the break active level can be programmed by the bredge bit in the breakcr register. when an active level is detect ed on the break pin, the ba bit is set and the break function is activated. in this case, t he pwm signals are forced to br eak value if respective oex bit is set in pwmcr register. software can set the ba bit to activate the break function without us ing the break pin. the bren1 and bren2 bits in the breaken register are used to enable the break activation on the 2 counters respectively. in dual ti mer mode, the break for pwm2 and pwm3 is enabled by the bren2 bit. in single timer mode, the bren1 bit enables the break for all pwm channels. dcr0+1 atr1 dcr0 t dt t dt t dt = dt[6:0] x t counter1 pwm 0 pwm 1 cntr1 ck_cntr1 t counter1 ovf pwm 0 pwm 1 if dte = 0 if dte = 1 counter = dcr0 counter = dcr1
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 88/226 when a break function is activate d (ba bit =1 and bren1/bren2 =1): the break pattern (pwm[3:0] bi ts in the breakcr) is forc ed directly on the pwmx output pins if respective oex is set. (after the inverter). the 12-bit pwm counter cntr1 is put to its reset value, i.e. 00h (if bren1 = 1). the 12-bit pwm counter cntr2 is put to its reset value,i.e. 00h (if bren2 = 1). atr1, atr2, preload and active dcrx are put to their reset values. counters stop counting. when the break function is deactivated after ap plying the break (ba bit goes from 1 to 0 by software), timer takes the control of pwm ports. note: the break function of the st7foxk2 is different from the break function of the st7foxf1/ST7FOXK1. refer to figure 41: st7foxf1/ST7FOXK1 block diagram of break function on page 88 and figure 42: st7foxk2 block diagram of break function on page 89 figure 41. st7foxf1/ST7FOXK1 block diagram of break function pwm0 pwm1 pwm2 pwm3 pwm0 pwm1 pwm2 pwm3 breakcr register break pin (inverters) pwm0 pwm1 pwm2 pwm3 bpen ba level selection brsel bredge breakcr register encntr2 bit bren1 bren2 breaken register pwm0/1 break enable pwm2/3 break enable oex
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 89/226 figure 42. st7foxk2 block diagram of break function output compare mode to use this function, load a 12-bit value in the preload dcrxh and dcrxl registers. when the 12-bit upcounter cntr1 reaches the value stored in the active dcrxh and dcrxl registers, the cmpfx bit in the pwmxcsr register is set and an interrupt request is generated if the cmpie bit is set. in single timer mode the output compare function is performed only on cntr1. the difference between both the modes is that, in single timer mode, cntr1 can be compared with any of the four dcr registers, and in du al timer mode, cntr1 is compared with dcr0 or dcr1 and cntr2 is co mpared with dcr2 or dcr3. note: 1 the output compare function is only available for dcrx values other than 0 (reset value). 2 duty cycle registers are buffered internally. th e cpu writes in preload duty cycle registers and these values are transferred in active duty cycle registers after an overflow event if the corresponding transfer bit (tranx bit) is set. output compare is done by comparing these active dcrx values with the counters. pwm0 pwm1 pwm2 pwm3 pwm0 pwm1 pwm2 pwm3 breakcr1 register break1 pin (inverters) pwm0 pwm1 pwm2 pwm3 bp1en ba1 level selection br1sel encntr2 bit bren1 bit pwm0/1 break enable pwm2/3 break enable oex br1edge comparator1 breakcr2 register swbr1 swbr2 - - bp2en ba2 br2sel br2edge break2 pin comparator2 level selection 0 0 1 1 bren2 bit
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 90/226 figure 43. block diagram of output compare mode (single timer) input capture mode the 12-bit aticr register is used to latch the value of the 12-bit free running upcounter cntr1 after a rising or falling edge is detected on the atic pin. when an input capture occurs, the icf bit is set and the aticr register contains the value of the free running upcounter. an ic interrupt is generated if the icie bit is set. the icf bit is reset by reading the aticrh/aticrl register when the icf bit is set. the aticr is a read only register and always contains the free running upcounter va lue which corresponds to the most recent input capture. any further input capture is inhibited while the icf bit is set. figure 44. block diagram of input capture mode dcrx output compare circuit counter 1 (atcsr) cmpie preload duty cycle reg0/1/2/3 active duty cycle regx cntr1 tran1 (atcsr2) ovf (atcsr) cmpfx (pwmxcsr) cmp request interrupt atcsr ck0 ck1 icie icf 12-bit autoreload register 12-bit upcounter1 f cpu atic 12-bit input capture register ic interrupt request atr1 aticr cntr1 (1 ms f ltimer @ 8mhz) timebase off
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 91/226 figure 45. input capture timing diagram long range input capture pulses that last more than 8 s can be measured with an accuracy of 4 s if f osc equals 8 mhz in the following conditions: the 12-bit at4 timer is clocked by the lite timer (rtc pulse: ck[1:0] = 01 in the atcsr register) the ics bit in the atcsr2 register is set so that the ltic pin is used to trigger the at4 timer capture. the signal to be captured is connected to ltic pin input capture registers lticr, aticrh and aticrl are read this configuration allows to cascade the lite timer and the 12-bit at4 timer to get a 20-bit input capture value. refer to figure 46 . figure 46. long range input capture block diagram counter1 t 01h f counter xxh 02h 03h 04h 05h 06h 07h 04h atic pin icf flag interrupt 08h 09h 0ah interrupt aticr read 09h lt i c at i c ics 1 0 12-bit input capture register off f cpu f lt i m e r 12-bit upcounter1 12-bit autoreload register 8-bit input capture register 8-bit timebase counter1 f osc/32 lticr cntr1 aticr atr1 8 lsb bits 12 msb bits lite timer 12-bit artimer 20 cascaded bits
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 92/226 since the input capture flags (icf) for both timers (at4 timer and lt timer) are set when signal transition occurs, software must mask one interrupt by clearing the corresponding icie bit before setting the ics bit. if the ics bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the input capture signal because of different values on ltic and atic. to avoid this situation, it is recommended to do as follows: 1. first, reset both icie bits. 2. then set the ics bit. 3. reset both icf bits. 4. and then set the icie bit of desired interrupt. computing a pulse length in long input capture mode is not straightforward since both timers are used. the following steps are required: 1. at the first input capture on the rising edge of the pulse, we assume that values in the registers are the following: ? lticr = lt1 ? aticrh = ath1 ? aticrl = atl1 ? hence aticr1 [11:0] = ath1 & atl1. refer to figure 47 on page 93 . 2. at the second input capture on the falling edge of the pulse, we assume that the values in the registers are as follows: ? lticr = lt2 ? aticrh = ath2 ? aticrl = atl2 ? hence aticr2 [11:0] = ath2 & atl2. now pulse width p between first capture and second capture is given by: where n is the number of overflows of 12-bit cntr1. p decimal f9 lt1 ? lt2 1 ++ () 0.004ms decimal fff n () n aticr2 aticr1 ? 1 ? ++ () 1ms + =
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 93/226 figure 47. long range input capture timing diagram f9h 00h lt1 f9h 00h lt2 ath1 & atl1 00h 0h lt1 ath1 lt2 ath2 f osc/32 tb counter1 cntr1 ltic lticr aticrh 00h atl1 atl2 aticrl aticr = aticrh[3:0] & aticrl[7:0] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ath2 & atl2 _ _ _
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 94/226 one pulse mode one pulse mode can be used to control pwm2/3 signal with an external ltic pin. this mode is available only in dual timer mode i.e. only for cntr2, when the op_en bit in pwm3csr register is set. one pulse mode is activated by the external lt ic input. the active edge of the ltic pin is selected by the opedge bit in the pwm3csr register. after getting the active edge of the ltic pin, cntr2 is reset (000h) and pwm3 is set to high. cntr2 starts counting from 000h, when it reaches the active dcr3 value then pwm3 goes low. till this time, any further transitions on the ltic signal will have no effect. if there are ltic transitions after cntr2 reaches dcr3 value, cntr2 is reset again and pwm3 goes high. if there is no ltic active edge, cntr2 counts until it reaches the atr2 value, then it is reset again and pwm3 is set to high. the counter again starts counting from 000h, when it reaches the active dcr3 value pwm3 goes low, the counter counts until it reaches atr2, it resets and pwm3 is set to high and so on. the same operation applies for pwm2, but in this case the comparison is done on dcr2. op_en and opedge bits take effect on the fly and are not synchronized with counter 2 overflow. the output bit op2/3 can be used to inverse the polarity of pwm2/3 in one-pulse mode. the update of these bits (op2/3) is synchronized with the counter 2 overflow, they will be updated if the tran2 bit is set. the time taken from activation of ltic input and cntr2 reset is between 1 and 2 t cpu cycles, that is, 125 ns to 250 ns (with 8-mhz f cpu ). lite timer input capture interrupt should be disabled while 12-bit artimer is in one pulse mode. this is to avoid spurious interrupts. the priority of the various conditions for pwm3 is the following: break > one-pulse mode with active ltic edge > forced overflow by s/w > one-pulse mode without active ltic edge > normal pwm operation. it is possible to update dcr2/3 and op2/3 at the counter 2 reset, the update is synchronized with the counter reset. this is managed by the overflow interrupt which is generated if counter is reset either due to atr match or active pulse at ltic pin. dcr2/3 and op2/3 update in one-pulse mode is per formed dynamically using a software force update. dcr3 update in this mode is not synchronized with any event. that may lead to a longer next pwm3 cycle duration than expected just after the change. in one pulse mode atr2 value must be greater than dcr2/3 value for pwm2/3. (opposite to normal pwm mode). if there is an active edge on the ltic pin after the counter has reset due to an atr2 match, then the timer again gets reset and appears as modified duty cycle depending on whether the new dcr value is less than or more than the previous value. the tran2 bit should be set along with the force2 bit with the same instruction after a write to the dcr register. atr2 value should be changed after an overflow in one pulse mode to avoid any irregular pwm cycle. when exiting from one pulse mode, the op_en bit in the pwm3csr register should be reset first and then the encntr2 bi t (if counter 2 must be stopped).
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 95/226 how to enter one pulse mode the steps required to enter one pulse mode are the following: 1. load atr2h/atr2l with required value. 2. load dcr3h/dcr3l for pwm3. atr2 value must be greater than dcr3. 3. set op3 in pwm3csr if polarity change is required. 4. select cntr2 by setting encntr2 bit in atcsr2. 5. set tran2 bit in atcsr2 to enable transfer. 6. "wait for overflow" by checking the ovf2 flag in atcsr2. 7. select counter clock using ck<1:0> bits in atcsr. 8. set op_en bit in pwm3csr to enable one-pulse mode. 9. enable pwm3 by oe3 bit of pwmcr. the "wait for overflow" in step 6 can be replaced by a forced update. follow the same procedure for pwm2 with the bits corresponding to pwm2. note: when break is applied in one-pulse mode, cntr2, dcr2/3 & atr2 registers are reset. so, these registers have to be initialized again when break is removed. figure 48. block diagram of one pulse mode figure 49. one pulse mode and pwm timing diagram ltic pin edge selection opedge pwm3csr register op_en 12-bit autoreload register 2 12-bit upcounter 2 12-bit active dcr2/3 generation pwm op2/3 pwm2/3 ovf at r 2 cntr2 lt i c pwm2/3 000 dcr2/3 000 dcr2/3 atr2 000 ovf atr2 dcr2/3 ovf atr2 dcr2/3 cntr2 lt ic pwm2/3 f counter2 f counter2 op_en=0 1) op_en=1 note 1: when op_en=0, ltic edges are not taken into account as the timer runs in pwm mode.
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 96/226 figure 50. dynamic dcr2/3 update in one pulse mode cntr2 lt i c 000 f counter2 op_en=1 (dcr2/3) old (dcr2/3) new dcr2/3 force2 tran2 fff (dcr3) old (dcr3) new atr2 000 pwm2/3 extra pwm3 period due to dcr3 update dynamically in one-pulse mode. 000
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 97/226 force update in order not to wait for the counter x overflow to load the value into active dcrx registers, a programmable counter x overflow is provided. for both counters, a separate bit is provided which when set, make the counters start with the overflow value, i.e. fffh. after overflow, the counters start counting from their respective auto reload register values. these bits are force1 and force2 in the atcsr2 register. force1 is used to force an overflow on counter 1 and, force2 is used for counter 2. these bits are set by software and reset by hardware after the respective counter overflow event has occurred. this feature can be used at any time. all related features such as pwm generation, output compare, input capture, one-pulse (refer to figure 50: dynamic dcr2/3 update in one pulse mode ) etc. can be used this way. figure 51. force overflow timing diagram 10.2.4 low power modes 10.2.5 interrupts note: the at4 ic is connected to an interrupt vector. the ovf event is mapped on a separate vector (see interrupts chapter). they generate an interrupt if the enable bit is set in the atcsr register and the interrupt mask in the cc register is reset (rim instruction). fff arrx e04 e03 f cntrx cntrx forcex force2 force1 atcsr2 register table 35. effect of low power modes on autoreload timer mode description wait no effect on at timer halt at timer halted. table 36. description of interrupt events interrupt event event flag enable control bit exit from wait exit from halt exit from active-halt overflow event ovf1 ovie1 yes no yes at4 ic event icf icie yes no no overflow event2 ovf2 ovie2 yes no no
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 98/226 10.2.6 register description timer control status register (atcsr) reset value: 0x00 0000 (x0h) bit 7 = reserved bit 6 = icf input capture flag this bit is set by hardware and cleared by software by reading the aticr register (a read access to aticrh or aticrl clears this flag). writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred bit 5 = icie ic interrupt enable bit this bit is set and cleared by software. 0: input capture interrupt disabled 1: input capture interrupt enabled bits 4:3 = ck[1:0] counter clock selection bits these bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. bit 2 = ovf1 overflow flag this bit is set by hardware and cleared by software by reading the atcsr register. it indicates the transition of the counter1 cntr1 from fffh to atr1 value. 0: no counter overflow occurred 1: counter overflow occurred bit 1 = ovfie1 overflow interrupt enable bit this bit is read/write by software and cleared by hardware after a reset. 0: overflow interrupt disabled. 1: overflow interrupt enabled. 7 0 0 icf icie ck1 ck0 ovf1 ovfie1 cmpie read / write table 37. counter clock selection counter clock selection ck1 ck0 off 0 0 selection forbidden 1 1 f lt i m e r (1 ms timebase @ 8 mhz) 0 1 f cpu 10
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 99/226 bit 0 = cmpie compare interrupt enable bit this bit is read/write by software and cleared by hardware after a reset. it can be used to mask the interrupt generated when any of the cmpfx bit is set. 0: output compare interrupt disabled. 1: output compare interrupt enabled. counter register 1 high (cntr1h) reset value: 0000 0000 (00h) counter register 1 low (cntr1l) reset value: 0000 0000 (00h) bits 15:12 = reserved bits 11:0 = cntr1[11:0] counter value this 12-bit register is read by software and cleared by hardware after a reset. the counter cntr1 increments continuously as soon as a counter clock is selected. to obtain the 12-bit value, software should read the counter value in two consecutive read operations. as there is no latch, it is recommended to read lsb first. in this case, cntr1h can be incremented between the two read operations and to have an accurate result when f timer =f cpu , special care must be taken when cntr1l values close to ffh are read. when a counter overflow occurs, the counter restarts from the value specified in the at r 1 r e g i s t e r. 15 8 0000 cntr1_ 11 cntr1_ 10 cntr1_9 cntr1_8 read only 7 0 cntr1_7 cntr1_6 cntr1_5 cntr1_4 cntr1_3 cntr1_2 cntr1_1 cntr1_0 read only
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 100/226 autoreload register (atr1h) reset value: 0000 0000 (00h) autoreload register (atr1l) reset value: 0000 0000 (00h) bits 11:0 = atr1[11:0] autoreload register 1: this is a 12-bit register which is written by software. the atr1 register value is automatically loaded into the upcounter cntr1 when an overflow occurs. the register value is used to set the pwm frequency. pwm output control register (pwmcr) reset value: 0000 0000 (00h) bits 7:0 = oe[3:0] pwmx output enable bits these bits are set and cleared by software and cleared by hardware after a reset. 0: pwm mode disabled. pwmx output alternate function disabled (i/o pin free for general purpose i/o) 1: pwm mode enabled pwmx control status register (pwmxcsr) reset value: 0000 0000 (00h) bits 7:4= reserved, must be kept cleared. bit 3 = op_en one pulse mode enable bit 15 8 0 0 0 0 atr11 atr10 atr9 atr8 read/write 7 0 at r 7 at r 6 at r 5 at r 4 at r 3 at r 2 at r 1 at r 0 read/write 7 0 0oe30oe20oe10oe0 read/write 7 0 0000op_enopedgeopxcmpfx read/write
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 101/226 this bit is read/write by software and cleared by hardware after a reset. this bit enables the one pulse feature for pwm2 and pwm3 (only available for pwm3csr) 0: one pulse mode disable for pwm2/3. 1: one pulse mode enable for pwm2/3. bit 2 = opedge one pulse edge selection bit this bit is read/write by software and cleared by hardware after a reset. this bit selects the polarity of the ltic signal for one pu lse feature. this bit will be effective only if op_en bit is set (only available for pwm3csr) 0: falling edge of ltic is selected. 1: rising edge of ltic is selected. bit 1 = opx pwmx output polarity bit this bit is read/write by software and cleared by hardware after a reset. this bit selects the polarity of the pwm signal. 0: the pwm signal is not inverted. 1: the pwm signal is inverted. bit 0 = cmpfx pwmx compare flag this bit is set by hardware and cleared by software by reading the pwmxcsr register. it indicates that the upcounter value matches th e active dcrx register value. 0: upcounter value does not match dcrx value. 1: upcounter value matches dcrx value. break control register 1 (breakcr1) reset value: 0000 0000 (00h) bit 7 = br1sel break 1 input selection bit ( only available on st7foxk2, reserved for st7foxf1/ST7FOXK1 ) this bit is read/write by software and cleared by hardware after reset. it selects the active break 1 signal from external break1 pin and the output of the comparator. 0: external break1 pin is selected for break mode. 1: comparator 1 output is selected for break mode. bit 6 = br1edge break 1 input edge selection bit ( bredge on st7foxf1/ST7FOXK1) this bit is read/write by software and cleared by hardware after reset. it selects the active level of break 1 signal. 0: low level of break 1selected as active level 1: high level of break 1selected as active level 7 0 br1sel br1edge ba1 bp1en pwm3 pwm2 pwm1 pwm0 read/write
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 102/226 bit 5 = ba1 break 1 active bit ( ba on st7foxf1/ST7FOXK1) this bit is read/write by software, cleared by hardware after reset and set by hardware when the active level defined by the br1e dge bit is applied on the break1 pin. it activates/deactivates the break 1function. 0: break 1not active 1: break 1active bit 4 = bp1en break 1pin enable bit ( bpen on st7foxf1/ST7FOXK1) this bit is read/write by software and cleared by hardware after reset. 0: break 1pin disabled 1: break 1pin enabled bits 3:0 = pwm[3:0] break pattern bits these bits are read/write by software and cleared by hardware after a reset. they are used to force the four pwmx output signals into a stable state when the break function is active and corresponding oex bit is set.
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 103/226 break control register 2 (breakcr2) reset value: 0000 0000 (00h) note: this register is available on st7foxk2 only bit 7 = br2sel break 2 input selection bit this bit is read/write by software and cleared by hardware after reset. it selects the active break 2 signal from external break2 pin and the output of the comparator. 0: external break2 pin is selected for break mode. 1: comparator 2 output is selected for break mode. bit 6 = br2edge break 2 input edge selection bit this bit is read/write by software and cleared by hardware after reset. it selects the active level of break 2 signal. 0: low level of break 2 selected as active level 1: high level of break 2 selected as active level bit 5 = ba2 break 2 active bit this bit is read/write by software, cleared by hardware after reset and set by hardware when the active level defined by the br2e dge bit is applied on the break2 pin. it activates/deactivates the break 2 function. 0: break 2 not active 1: break 2 active bit 4 = bp2en break 2 pin enable bit this bit is read/write by software and cleared by hardware after reset. 0: break2 pin disabled 1: break2 pin enabled bits 3:2 = reserved, must be kept cleared bit 1 = swbr2 switch break for counter 2 bit this bit is read/write by software. while bren2 is set, it selects ba1 or ba2 to control pwm2/3 if encntr2 bit is set. 0: ba1 selected 1: ba2 selected bit 0 = swbr1 switch break for counter 1 bit this bit is read/write by software. while bren1 is set, it selects ba1 or ba2 to control pwm0/1 by default and also pwm2/3 if encntr2 bit is reset. 0: ba1 selected 1: ba2 selected 7 0 br2sel br2edge ba2 bp2en - - swbr2 swbr1 read/write
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 104/226 pwmx duty cycle register high (dcrxh) reset value: 0000 0000 (00h) bits 15:12 = reserved. pwmx duty cycle register low (dcrxl) reset value: 0000 0000 (00h) bits 11:0 = dcrx[11:0] pwmx duty cycle value: this 12-bit value is written by software. it defines the duty cycle of the corresponding pwm output signal (see figure 38 ). in pwm mode (oex=1 in the pwmcr register) the dcr[11:0] bits define the duty cycle of the pwmx output signal (see figure 38 ). in output compare mode, they define the value to be compared with the 12-bit upcounter value. input capture register high (aticrh) reset value: 0000 0000 (00h) bits 15:12 = reserved. 15 8 0 0 0 0 dcr11 dcr10 dcr9 dcr8 read/write 7 0 dcr7 dcr6 dcr5 dcr4 dcr3 dcr2 dcr1 dcr0 read/write 15 8 0000icr11icr10icr9icr8 read only
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 105/226 input capture register low (aticrl) reset value: 0000 0000 (00h) bits 11:0 = icr[11:0] input capture data . this is a 12-bit register which is readable by software and cleared by hardware after a reset. the aticr register contains captured the value of the 12-bit cntr1 register when a rising or falling edge occurs on th e atic or ltic pin (depending on ics). capture will only be performed when the icf flag is cleared. break enable register (breaken) reset value: 0000 0011 (03h) bits 7:2 = reserved, must be kept cleared. bit 1 = bren2 break enable for counter 2 bit this bit is read/write by software. it enables the break functionality for counter2 if ba bit is set in breakcr. it controls pwm2/3 if encntr2 bit is set. 0: no break applied for cntr2 1: break applied for cntr2 bit 0 = bren1 break enable for counter 1 bit this bit is read/write by software. it enables the break functionality for counter1. if ba bit is set, it controls pwm0/1 by default, and controls pwm2/3 also if encntr2 bit is reset. 0: no break applied for cntr1 1: break applied for cntr1 7 0 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 read only 7 0 000000bren2bren1 read/write
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 106/226 timer control register 2 (atcsr2) reset value: 0000 0011 (03h) bit 7 = force2 force counter 2 overflow bit this bit is read/set by software. when set, it loads fffh in the cntr2 register. it is reset by hardware one cpu clock cycle after counter 2 overflow has occurred. 0 : no effect on cntr2 1 : loads fffh in cntr2 note: this bit must not be reset by software bit 6 = force1 force counter 1 overflow bit this bit is read/set by software. when set, it loads fffh in cntr1 register. it is reset by hardware one cpu clock cycle after counter 1 overflow has occurred. 0 : no effect on cntr1 1 : loads fffh in cntr1 note: this bit must not be reset by software bit 5 = ics input capture shorted bit this bit is read/write by software. it allows the attimer cntr1 to use the ltic pin for long input capture. 0 : atic for cntr1 input capture 1 : ltic for cntr1 input capture bit 4 = ovfie2 overflow interrupt 2 enable bit this bit is read/write by software and controls the overflow interrupt of counter2. 0: overflow interrupt disabled. 1: overflow interrupt enabled. bit 3 = ovf2 overflow flag this bit is set by hardware and cleared by software by reading the atcsr2 register. it indicates the transition of the counter2 from fffh to atr2 value. 0: no counter overflow occurred 1: counter overflow occurred bit 2 = encntr2 enable counter2 for pwm2/3 this bit is read/write by software and switches the pwm2/3 operation to the cntr2 counter. if this bit is set, pwm2/3 will be generated using cntr2. 0: pwm2/3 is generated using cntr1. 1: pwm2/3 is generated using cntr2. note: counter 2 gets frozen when the encntr2 bit is reset. when encntr2 is set again, the counter will restart from the last value. 7 0 force2 force1 ics ovfie2 ovf2 encntr2 tran2 tran1 read/write
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 107/226 bit 1= tran2 transfer enable2 bit this bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. it controls the transfers on cntr2. it allows the value of the preload dcrx registers to be transferred to the active dcrx registers after the next overflow event. the opx bits are transferred to the shadow opx bits in the same way. note: 1 dcr2/3 transfer will be controlled us ing this bit if encntr2 bit is set. 2 this bit must not be reset by software bit 0 = tran1 transfer enable 1 bit this bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. it controls the transfers on cntr1. it allows the value of the preload dcrx registers to be transfer red to the active dcrx registers after the next overflow event. the opx bits are transferred to the shadow opx bits in the same way. note: 1 dcr0,1 transfers are always controlled using this bit. 2 dcr2/3 transfer will be controlled usin g this bit if encntr2 is reset. 3 this bit must not be reset by software autoreload register 2 (atr2h) reset value: 0000 0000 (00h) autoreload register (atr2l) reset value: 0000 0000 (00h) bits 11:0 = atr2[11:0] autoreload register 2 this is a 12-bit register which is written by software. the atr2 register value is automatically loaded into the upcounter cntr2 when an overflow of cntr2 occurs. the register value is used to set the pwm2/pwm3 frequency when encntr2 is set. 15 8 0000atr11atr10atr9atr8 read/write 7 0 at r 7 at r 6 at r 5 at r 4 at r 3 at r 2 at r 1 at r 0 read/write
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 108/226 dead time generator register (dtgr) reset value: 0000 0000 (00h) bit 7 = dte dead time enable bit this bit is read/write by software. it enables a dead time generation on pwm0/pwm1. 0: no dead time insertion. 1: dead time insertion enabled. bits 6:0 = dt[6:0] dead time value these bits are read/write by software. they define the dead time inserted between pwm0/pwm1. dead time is calculated as follows: dead time = dt[6:0] x tcounter1 note: if dte is set and dt[6:0]=0, pwm ou tput signals will be at their reset state. 7 0 dte dt6 dt5 dt4 dt3 dt2 dt1 dt0 read/write table 38. register mapping and reset values add. (hex) register label 76543 210 0011 atcsr reset value 0 icf 0 icie 0 ck1 0 ck0 0 ovf1 0 ovfie1 0 cmpie 0 0012 cntr1h reset value 0000 cntr1_1 1 0 cntr1_1 0 0 cntr1_9 0 cntr1_ 8 0 0013 cntr1l reset value cntr1_7 0 cntr1_8 0 cntr1_ 7 0 cntr1_6 0 cntr1_3 0 cntr1_2 0 cntr1_1 0 cntr1_ 0 0 0014 atr1h reset value 0000 at r 1 1 0 at r 1 0 0 at r 9 0 at r 8 0 0015 atr1l reset value at r 7 0 at r 6 0 at r 5 0 at r 4 0 at r 3 0 at r 2 0 at r 1 0 at r 0 0 0016 pwmcr reset value 0 oe3 0 0 oe2 0 0 oe1 0 0 oe0 0 0017 pwm0csr reset value 00000 0 op0 0 cmpf0 0 0018 pwm1csr reset value 00000 0 op1 0 cmpf1 0 0019 pwm2csr reset value 00000 0 op2 0 cmpf2 0 001a pwm3csr reset value 0000 op_en 0 opedge 0 op3 0 cmpf3 0 001b dcr0h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 109/226 001c dcr0l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 001d dcr1h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 001e dcr1l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 001f dcr2h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 0020 dcr2l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 0021 dcr3h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 0022 dcr3l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 0023 aticrh reset value 0000 icr11 0 icr10 0 icr9 0 icr8 0 0024 aticrl reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 0025 atcsr2 reset value force2 0 force1 0 ics 0 ovfie2 0 ovf2 0 encntr2 0 tran2 1 tran1 1 0026 breakcr1 (1) reset value 0 bredge 0 ba 0 bpen 0 pwm3 0 pwm2 0 pwm1 0 pwm0 0 0027 atr2h reset value 0000 at r 1 1 0 at r 1 0 0 at r 9 0 at r 8 0 0028 atr2l reset value at r 7 0 at r 6 0 at r 5 0 at r 4 0 at r 3 0 at r 2 0 at r 1 0 at r 0 0 0029 dtgr reset value dte 0 dt6 0 dt5 0 dt4 0 dt3 0 dt2 0 dt1 0 dt0 0 002a breaken reset value 0 0 0 0 0 0 bren2 1 bren1 1 002b reserved area 002c breakcr2 (2) reset value br2sel 0 br2edge 0 ba2 0 bp2en 0 00 swbr2 0 swbr1 0 1. 2. table 38. register mapping and reset values (continued) add. (hex) register label 76543 210
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 110/226 10.3 lite timer 2 (lt2) 10.3.1 introduction the lite timer can be used for general-purpose timing functions. it is based on two free- running 8-bit upcounters, a watchdog function and an 8-bit input capture register. 10.3.2 main features real-time clock ? one 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 mhz f osc ) ? one 8-bit upcounter with autoreload and programmable timebase period from 4s to 1.024 ms in 4 s increments (@ 8 mhz f osc ) ? 2 maskable timebase interrupts input capture ? 8-bit input capture register (lticr) maskable interrupt with wakeup from halt mode capability watchdog ? enabled by hardware or software (configurable by option byte) ? optional reset on halt instruction (configurable by option byte) ? automatically resets the device unless disable bit is refreshed ? software reset (forced watchdog reset) ? watchdog reset status flag
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 111/226 figure 52. lite timer 2 block diagram 10.3.3 functional description timebase counter 1 the 8-bit value of counter 1 cannot be read or written by software. after an mcu reset, it starts incrementing from 0 at a frequency of f osc /32. an overflow event occurs when the counter rolls over from f9h to 00h. if f osc = 8 mhz, then the time period between two counter overflow events is 1 ms. this period can be doubled by setting the tb bit in the ltcsr1 register. when counter 1 overflows, the tb1f bit is set by hardware and an interrupt request is generated if the tb1ie bit is set. the tb1f bit is cleared by software reading the ltcsr1 register. input capture the 8-bit input capture register is used to latch the free-running upcounter (counter 1) 1 after a rising or falling edge is detected on the ltic pin. when an input capture occurs, the icf bit is set and the lticr register contains the counter 1 value. an interrupt is generated if the icie bit is set. the icf bit is cleared by reading the lticr register. the lticr is a read-only register and always contains the data from the last input capture. input capture is inhibited if the icf bit is set. ltcsr1 8-bit timebase /2 8-bit f ltimer 8 ltic f osc /32 tb1f tb1ie tb icf icie lttb1 interrupt request ltic interrupt request lticr input capture register 1 0 1 or 2 ms timebase (@ 8 mhz f osc ) to 12-bit at timer f ltimer ltcsr2 tb2f 0 tb2ie 0 lttb2 8-bit timebase 0 0 8-bit autoreload register 8 ltcntr ltarr counter 2 counter 1 0 0 interrupt request
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 112/226 timebase counter 2 counter 2 is an 8-bit autoreload upcounter. it can be read by accessing the ltcntr register. after an mcu reset, it increments at a frequency of f osc /32 starting from the value stored in the ltarr register. a counter overflow event occurs when the counter rolls over from ffh to the ltarr reload value. software can write a new value at any time in the ltarr register, this value will be automatically loaded in the co unter when the next overflow occurs. when counter 2 overflows, the tb2f bit in the ltcsr2 register is set by hardware and an interrupt request is generated if the tb2ie bit is set. the tb2f bit is cleared by software reading the ltcsr2 register. figure 53. input capture timing diagram watchdog when enabled using the wdge bit, the watchdog generates a reset after 2 ms (@ = 8 mhz f osc ). to prevent this watchdog reset occurring, software must set the wdgd bit. the wdgd bit is cleared by hardware after t wdg . this means that software must write to the wdgd bit at regular intervals to prevent a watchdog reset occurring. refer to figure 54 . note: software can use the timebase feature to set the wdgd bit at 1 or 2 ms intervals. a watchdog reset can be forced at any time by setting the wdgrf bit. the wdgrf bit also acts as a flag, indicating that the watchdog was the source of the reset. it is automatically cleared after it has been read. hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdge bit in the ltcsr1 is not used. refer to the option byte description. using halt mode with the watchdog (option) if the watchdog reset on halt option is not selected by option byte, the halt mode can be used when the watchdog is enabled. 04h 8-bit counter 1 t 01h f osc /32 xxh 02h 03h 05h 06h 07h 04h ltic pin icf flag lticr register cleared 4s (@ 8 mhz f osc ) f cpu by s/w 07h reading ltic register
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 113/226 in this case, the halt instruction stops the oscillator. when the oscillator is stopped, the lite timer stops counting and is no longer able to generate a watchdog reset until the microcontroller receives an external interrupt or a reset. if an external interrupt is received, the wdg restarts counting after 4096 cpu clocks. if a reset is generated, the watchdog is disabled (reset state). recommendations make sure that an external event is available to wake up the microcontroller from halt mode. before executing the halt instruction, refresh the wdgd bit, to avoid an unexpected watchdog reset immediately after waking up the microcontroller. when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. for the same reason, reinitialize the level sens itiveness of each external interrupt as a precautionary measure. figure 54. watchdog timing diagram 10.3.4 low power modes t wdg f wdg internal watchdog reset wdgd bit software sets wdgd bit hardware clears wdgd bit watchdog reset (2ms @ 8mhz f osc ) table 39. effect of low power modes on lite timer 2 mode description slow no effect on lite timer (this peripheral is driven directly by f osc /32) wait no effect on lite timer active halt no effect on lite timer halt lite timer stops counting
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 114/226 10.3.5 interrupts the tbxf and icf interrupt events are connected to separate interrupt vectors (see section 7: interrupts ). they generate an interrupt if the enable bit is set in the ltcsr1 or ltcsr2 register and the interrupt mask in the cc register is reset (rim instruction). 10.3.6 register description lite timer control/status register 2 (ltcsr2) reset value: 0000 0000 (00h) bits 7:2 = reserved, must be kept cleared. bit 1 = tb2ie timebase 2 interrupt enable bit this bit is set and cleared by software. 0: timebase (tb2) interrupt disabled 1: timebase (tb2) interrupt enabled bit 0 = tb2f timebase 2 interrupt flag this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter 2 overflow 1: a counter 2 overflow has occurred table 40. description of interrupt events interrupt event event flag enable control bit exit from wait exit from active halt exit from halt timebase 1 event tb1f tb1ie ye s ye s no timebase 2 event tb2f tb2ie no ic event icf icie no 7 0 000000tb2ietb2f read / write
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 115/226 lite timer autoreload register (ltarr) reset value: 0000 0000 (00h) bits 7:0 = ar[7:0] counter 2 reload value these bits register is read/write by software. the ltarr value is automatically loaded into counter 2 (ltcntr) when an overflow occurs. lite timer counter 2 (ltcntr) reset value: 0000 0000 (00h) bits 7:0 = cnt[7:0] counter 2 reload value this register is read by software. the ltarr value is automatically loaded into counter 2 (ltcntr) when an overflow occurs. lite timer control/status register (ltcsr1) reset value: 0x00 0000 (x0h) bit 7 = icie interrupt enable bit this bit is set and cleared by software. 0: input capture (ic) interrupt disabled 1: input capture (ic) interrupt enabled bit 6 = icf input capture flag this bit is set by hardware and cleared by software by reading the lticr register. writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred note: after an mcu reset, software must initialize the icf bit by reading the lticr register 7 0 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 read / write 7 0 cnt7 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 read only 7 0 icie icf tb tb1ie tb1f read / write
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 116/226 bit 5 = tb timebase period selection bit this bit is set and cleared by software. 0: timebase period = t osc * 8000 (1 ms @ 8 mhz) 1: timebase period = t osc * 16000 (2 ms @ 8 mhz) bit 4 = tb1ie timebase interrupt enable bit this bit is set and cleared by software. 0: timebase (tb1) interrupt disabled 1: timebase (tb1) interrupt enabled bit 3 = tb1f timebase interrupt flag this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter overflow 1: a counter overflow has occurred bits 2:0 = reserved, must be kept cleared. lite timer input capture register (lticr) reset value: 0000 0000 (00h) bits 7:0 = icr[7:0] input capture value these bits are read by software and cleared by hardware after a reset. if the icf bit in the ltcsr is cleared, the value of the 8-bit up-c ounter will be captured when a rising or falling edge occurs on the ltic pin. 7 0 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 read only table 41. lite timer register mapping and reset values address (hex.) register label 76543210 0c ltcsr2 reset value 000000 tb2ie 0 tb2f 0 0d ltarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 0e ltcntr reset value cnt7 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 0f ltcsr1 reset value icie 0 icf x tb 0 tb1ie 0 tb1f 0 000 10 lticr reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 117/226 10.4 16-bit timer 10.4.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input signals ( input capture ) or generation of up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the cpu clock prescaler. 10.4.2 main features programmable prescaler: f cpu divided by 2, 4 or 8. overflow status flag and maskable interrupt external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge output compare functions with ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt input capture functions with ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one pulse mode reduced power mode 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk) note: some timer pins may not be available (not bonded) in some devices. refer to section 2: pin description on page 15 . the block diagram is shown in figure 55 . when reading an input signal on a non-bonded pin, the value is always ?1?. 10.4.3 functional description counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high and low.
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 118/226 counter register (cr) counter high register (chr) is the most significant byte (msb). counter low register (clr) is th e least significant byte (lsb). alternate counter register (acr) alternate counter high register (achr) is the msb. alternate counter low register (aclr) is the lsb. these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see 16-bit read sequence (from either the counter register or the alternate counter register) on page 120 ). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit timer). the reset value of both co unters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bi ts of the cr2 register, as illustrated in ta bl e 3 7 . the value in the counter register repeats every 131 072, 262 144 or 524 288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency.
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 119/226 figure 55. timer block diagram 1. if ic, oc and to interrupt requests have separate vectors then the last or is not present (see table 17: st7foxf1/ST7FOXK1 interrupt mapping ) output compare register 1 output compare circuit overflow detect circuit 1/2 1/4 1/8 8-bit buffer internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie latch2 8 low 16 8 high 16 16 16 16 cr1 (control register 1) cr 2 (control register 2) csr (control/status register ) 6 16 8 high exedg timer internal bus input capture register 1 cc[1:0] counter pin pin pin register (1) 16-bit timer peripheral interface 8 low 8 high 8 low 8 high 8 low 8 high 8 low output compare register 2 input capture register 2 alternate counter register edge detect circuit 2 edge detect circuit 1 icap2 pin ocmp2 pin
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 120/226 16-bit read sequence (from either the counter register or the alternate counter register) figure 56. 16-bit read sequence the user must read the msb first, then the lsb value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the msb several times. after a complete reading sequence, if only the clr register or aclr register are read, they return the lsb of the count value at the time of the read. whatever the timer mode used (input capture, output compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set. a timer interrupt is generated if: ? toie bit of the cr1 register is set and ? i bit of the cc register is cleared. if one of these conditions is false, the interr upt remains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (device awakened by an interrupt) or from the reset count (device awakened by a reset). external clock the external clock (where available) is selected if cc0 = 1 and cc1 = 1 in cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the external clock pin extclk that triggers the free running counter. the counter is synchronize d with the falling edge of the internal cpu clock. read msb at t0 returns the buffered lsb value at t0 at t0 + ? t other instructions beginning of the sequence sequence completed lsb is buffered read lsb
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 121/226 a minimum of four falling edges of the cpu clock must occur betw een two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the cpu clock frequency. figure 57. counter timing diagram, internal clock divided by 2 figure 58. counter timing diagram, internal clock divided by 4 figure 59. counter timing diagram, internal clock divided by 8 note: the device is in rese t state when the internal reset signal is high, when it is low the device is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 122/226 input capture in this section, the index, i , may be 1 or 2 because there are two input capture functions in the 16-bit timer. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free-running counter after a transition detected by the icap i pin (see below). ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure to use the input capture function, select the following in the cr2 register: select the timer clock (cc[1:0]). select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input). select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input). when an input capture occurs: the icf i bit is set the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 61 ). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. otherwise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. by reading the sr register while the icf i bit is set. 2. by accessing (reading or writing) the ic i lr register. note: 1 after reading the icihr regist er, transfer of input capture data is inhibited and icfi is never set until the icilr register is also read. 2 the icir register contains the free running counter value which corresponds to the most recent input capture. 3 the two input capture functions can be used together even if the timer also uses the two output compare functions. 4 in one pulse mode and pwm mode only the input capture 2 can be used. 5 the alternate inputs (icap1 and icap2) are always directly connected to the timer. so any transitions on these pins activate the input capture function. moreover if one of the icapi pin is configured as an input and the second one as an output, an interrupt can be generated if msb lsb icir ic i hr ic i lr
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 123/226 the user toggle the output pin and if the icie bit is set. this can be avoided if the input capture function i is disabled by reading the icihr (see note 1). 6 the tof bit can be used with interrupt in order to measure event that go beyond the timer range (ffffh). figure 60. input capture block diagram figure 61. input capture timing diagram 1. the active edge is the rising edge. 2. the time between an event on the icapi pin and the appearance of the corresponding flag is from 2 to 3 cpu clock cycles. this depends on the moment when the icap ev ent happens relative to the timer clock. icie cc0 cc1 16-bit free running counter iedg1 cr1 (control register 1) cr2 (control register 2) icf2 icf1 0 0 0 sr (status register) iedg2 icap1 edge detect circuit 2 16-bit ic2r register pin icap2 pin edge detect circuit 1 ic1r register ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 124/226 output compare in this section, the index, i , may be 1 or 2 because there are two output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output compare register and the free running counter, the output compare function: assigns pins with a programmable value if the ocie bit is set sets a flag in the status register generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the following in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. select the timer clock (cc[1:0]) (see : timer a control register 2 (tacr2) on page 134 ). in the cr1 register select the following: select the olvl i bit to be applied to the ocmp i pins after the match occurs. set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: set the ocf i bit. the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the cc register (cc). msb lsb oc i roc i hr oc i lr
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 125/226 the oc i r register value required for a specific timing application can be calculated using the following formula: equation 1 where: if the timer clock is an external clock, the formula is: equation 2 where: clearing the output compare interrupt request (that is, clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. accessing (reading or writing) the oc i lr register. the following procedure is recommended to prevent the ocf i bit from being set between the time it is read and the time it is written to the oc i r register: write to the oc i hr register (further compares are inhibited). read the sr register (first step in the clearance of the ocf i bit, which may be already set). write to the oc i lr register (enables the output compare function and clears the ocf i bit). note: 1 after a processor write cycle to the ocihr r egister, the output compar e function is inhibited until the ocilr regist er is also written. 2 if the ocie bit is not set, the ocmpi pin is a general i/o port and the olvli bit does not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3 in both internal and external clock modes, ocfi and ocmpi are set while the counter value equals the ocir register value (see figure 63 for an example with f cpu /2 and figure 64 for an example with f cpu /4). this behavior is the same in opm or pwm mode. 4 the output compare functions can be used both for generating external events on the ocmpi pins even if the input capture mode is also used. 5 the value in the 16-bit oc i r register and the olvi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. ? t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see : timer a control register 2 (tacr2) on page 134 ) ? t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) ? oc i r= ? t * f cpu presc ? oc i r= ? t * f ext
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 126/226 forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit = 1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in both one pulse mode and pwm mode. figure 62. output compare block diagram figure 63. output compare timing diagram, f timer =f cpu /2 output compare circuit oc1r register oc1e cc0 cc1 oc2e olvl1 olvl2 ocie 0 0 0 ocf2 ocf1 16-bit ocmp1 latch 1 latch 2 oc2r register pin folv2 folv1 ocmp2 pin 16-bit free running counter cr1 (control register 1) cr2 (control register 2) sr (status register) 16-bit 16-bit internal cpu clock timer clock counter register output compare register i (ocri) output compare flag i (ocfi) ocmpi pin (olvli = 1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 127/226 figure 64. output compare timing diagram, f timer =f cpu /4 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure 1. load the oc1r register with the value corresponding to the length of the pulse (see equation 3 below). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then dedicated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see : timer a control register 2 (tacr2) on page 134 ). internal cpu clock timer clock counter register output compare register i (ocri) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmpi pin (olvli = 1) output compare flag i (ocfi)
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 128/226 figure 65. one pulse mode sequence when a valid event occurs on the icap1 pin, the counter value is loaded in the icr1 register. the counter is then initialized to fffch, the olvl2 bit is output on the ocmp1 pin and the icf1 bit is set. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. accessing (reading or writing) the ic i lr register. the oc1r register value required for a specif ic timing application can be calculated using the following formula: equation 3 where: if the timer clock is an external clock the formula is: equation 4 where: when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 66 ). t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on the cc[1:0] bits, see : timer a control register 2 (tacr2) on page 134 ) t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) occurs on counter = oc1r ocmp1 = olvl1 when when event icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter oc i r value = t * f cpu presc - 5 oc i r= t * f ext -5
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 129/226 note: 1 the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3 if olvl1 = olvl2 a continuous signal is seen on the ocmp1 pin. 4 the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5 when one pulse mode is used oc1r is dedic ated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level olvl2 is dedicated to the one pulse mode. figure 66. one pulse mode timing example 1. iedg1 = 1, oc1r = 2ed0h, olvl1 = 0, olvl2 = 1 figure 67. pulse width modu lation mode timing example 1. oc1r = 2ed0h, oc2r = 34e2, olvl1 = 0, olvl2 = 1 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r register, and so this functionality can no t be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values written in the oc1r and oc2r registers are loaded in their respective shadow registers (double buffer) only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). the shadow registers contain the reference values for comparison in pwm ?double buffering? mode. counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 01f8 01f8 2ed3 ic1r counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 fffc fffd fffe 2ed0 2ed1 2ed2
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 130/226 note: there is a locking mechanism for transferring the ocir value to the buffer. after a write to the ocihr register, transfer of the new compare value to the buffer is inhibited until ocilr is also written. unlike in output compare mode, the compare function is always enabled in pwm mode. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corresponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corresponding to the period of the pulse if (olvl1 = 0 and olvl2 = 1) using equation 5 . 3. select the following in the cr1 register: using the olvl1 bit, select the level to be applied to the ocmp1 pin after a successful comparison with oc1r register. using the olvl2 bit, select the level to be applied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: set oc1e bit: the ocmp1 pin is then dedi cated to the output compare 1 function. set the pwm bit. select the timer clock (cc[1:0]) (see : timer a control register 2 (tacr2) on page 134 ). figure 68. pulse width modulation cycle if olvl = 1 and olvl2 = 0 the length of the positive pulse is the difference between the oc2r and oc1r registers. if olvl1 = olvl2 a continuous signal is seen on the ocmp1 pin. counter ocmp1 = olvl2 ocmp1 = olvl1 when =oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set counter when = oc2r
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 131/226 the oc i r register value required for a specific timing application can be calculated using the following formula: equation 5 where: if the timer clock is an external clock the formula is: equation 6 where: the output compare 2 event causes the counter to be initialized to fffch (see figure 67 ) note: 1 the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 2 the icf1 bit is set by hardware when the c ounter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 3 in pwm mode the icap1 pin can not be used to perform input capture because it is disconnected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 4 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 10.4.4 low power modes t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see : timer a control register 2 (tacr2) on page 134 ) t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) oc i r value = t * f cpu presc - 5 oc i r= t * f ext -5 table 42. effect of low power modes on 16-bit timer mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the device is woken up by an interrupt with ?exit from halt mode? capability or from the counter reset value when the device is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequently, when the device is wok en up by an interrupt with ?exit from halt mode? capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register.
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 132/226 10.4.5 interrupts 10.4.6 summary of 16-bit timer modes table 43. 16-bit timer interrupt control/wakeup capability (1) 1. the 16-bit timer interrupt events are connec ted to the same interrupt vector (see section 7: interrupts ). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie ye s n o input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie ye s n o output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no table 44. summary of 16-bit timer modes modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1) and/or (2) 1. see note 4 in one pulse mode on page 127 . 2. see note 5 in one pulse mode on page 127 . yes yes yes yes output compare (1) and/or (2) yes yes yes yes one pulse mode no not recommended (1) no partially (2) pwm mode no not recommended (3) 3. see note 4 in pulse width modulation mode on page 129 . no no
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 133/226 10.4.7 16-bit timer registers each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. tima control register 1 (tacr1) reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable 0: interrupt is inhibited 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set bit 6 = ocie output compare interrupt enable 0: interrupt is inhibited 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set bit 5 = toie timer overflow interrupt enable 0: interrupt is inhibited 1: a timer interrupt is enabled whenever the tof bit of the sr register is set bit 4 = folv2 forced output compare 2 this bit is set and cleared by software. 0: no effect on the ocmp2 pin 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison bit 3 = folv1 forced output compare 1 this bit is set and cleared by software. 0: no effect on the ocmp1 pin 1: forces olvl1 to be copied to the ocmp 1 pin, if the oc1e bit is set and even if there is no successful comparison bit 2 = olvl2 output level 2 this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r register and ocxe is set in the cr2 re gister. this value is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. 7 0 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 read / write
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 134/226 bit 1 = iedg1 input edge 1 this bit determines which type of level transition on the icap1 pin triggers the capture. 0: a falling edge triggers the capture 1: a rising edge triggers the capture bit 0 = olvl1 output level 1 the olvl1 bit is copied to the ocmp1 pin whenever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. timer a control register 2 (tacr2) reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output compare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o) 1: ocmp1 pin alternate function enabled bit 6 = 0c2e output compare 2 pin enable this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output compare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o) 1: ocmp2 pin alternate function enabled bit 5 = opm one pulse mode 0: one pulse mode is not active 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation 0: pwm mode is not active 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r register. bits 3:2 cc[1:0] clock control the timer clock mode depends on the following bits: 00: timer clock = f cpu /4 01: timer clock = f cpu /2 7 0 oc1e oc2e opm pwm cc[1:0] iedg2 exedg read / write
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 135/226 10: timer clock = f cpu /8 11: timer clock = external clock (where available) note: if the external clock pin is not available, programming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2 this bit determines which type of level transition on the icap2 pin triggers the capture. 0: a falling edge triggers the capture 1: a rising edge triggers the capture bit 0 = exedg external clock edge this bit determines which type of level transition on the external clock pin extclk triggers the counter register. 0: a falling edge triggers the counter register 1: a rising edge triggers the counter register timer a control/status register (tacsr) reset value: 0000 0000 (00h) the 3 least significant bits are not used. bit 7 = icf1 input capture flag 1 0: no input capture (reset value) 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1 0: no match (reset value) 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. bit 5 = tof timer overflow flag 0: no timer overflow (reset value) 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. 7 0 icf1 ocf1 tof icf2 ocf2 timd reserved read only
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 136/226 bit 4 = icf2 input capture flag 2 0: no input capture (reset value) 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2 0: no match (reset value) 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. bit 2 = timd timer disable this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disables the output functions (ocmp1 and ocmp2 pins) to reduce power consumption. access to th e timer registers is still av ailable, allowing the timer configuration to be chan ged while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled bits 1:0 = reserved, must be kept cleared timer a input capture 1 high register (taic1hr) reset value: undefined this is an 8-bit read-only register that contains the high part of the counter value (transferred by the input capture 1 event). timer a input capture 1 low register (taic1lr) reset value: undefined this is an 8-bit read-only register that contains the low part of the counter value (transferred by the input capture 1 event). 7 0 msb lsb read only 7 0 msb lsb read only
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 137/226 timer a output compare 1 high register (taoc1hr) reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. timer a output compare 1 low register (taoc1lr) reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. output compare 2 high register (oc2hr) reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 7 0 msb lsb read / write 7 0 msb lsb read / write 7 0 msb lsb read / write 7 0 msb lsb read / write
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 138/226 counter high register (chr) reset value: 1111 1111 (ffh) this is an 8-bit read-only register that contains the high part of the counter value. counter low register (clr) reset value: 1111 1100 (fch) this is an 8-bit read-only register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. alternate counter high register (achr) reset value: 1111 1111 (ffh) this is an 8-bit read-only register that contains the high part of the counter value. alternate counter low register (aclr) reset value: 1111 1100 (fch) this is an 8-bit read-only register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. 7 0 msb lsb read only 7 0 msb lsb read only 7 0 msb lsb read only 7 0 msb lsb read only
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 139/226 input capture 2 high register (ic2hr) reset value: undefined this is an 8-bit read-only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) reset value: undefined this is an 8-bit read-only register that contains the low part of the counter value (transferred by the input capture 2 event). 10.4.8 16-bit timer regist er map and reset values 7 0 msb lsb read only 7 0 msb lsb read only table 45. 16-bit timer register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 55 tacr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 56 tacr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 57 tac s r reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 timd 0 - 0 - 0 58 taichr1 reset value msb - ------ lsb - 59 ta i c l r 1 reset value msb - ------ lsb - 5a taochr1 reset value msb - ------ lsb - 5b tao c l r 1 reset value msb - ------ lsb - 5c tachr reset value msb 111 1 1 1 1 lsb 1 5d tac l r reset value msb 111 1 1 1 0 lsb 0
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 140/226 5e ta ac h r reset value msb 111 1 1 1 1 lsb 1 5f ta ac l r reset value msb 111 1 1 1 0 lsb 0 60 taichr2 reset value msb - ------ lsb - 61 ta i c l r 2 reset value msb - ------ lsb - 62 taochr2 reset value msb - ------ lsb - 63 tao c l r 2 reset value msb - ------ lsb - table 45. 16-bit timer register map and reset values (continued) address (hex.) register label 7 6 5 4 3 2 1 0
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 141/226 10.5 i 2 c bus interface (i 2 c) 10.5.1 introduction the i 2 c bus interface serves as an interface between the microcontroller and the serial i 2 c bus. it provides both multimaster and slave functions, and controls all i 2 c bus-specific sequencing, protocol, arbitration and timing. it supports fast i 2 c mode (400 khz). 10.5.2 main features parallel-bus/i 2 c protocol converter multi-master capability 7-bit/10-bit addressing transmitter/receiver flag end-of-byte transmission flag transfer problem detection i 2 c master features: clock generation i 2 c bus busy flag arbitration lost flag end of byte transmission flag transmitter/receiver flag start bit detection flag start and stop generation i 2 c slave features: stop bit detection i 2 c bus busy flag detection of misplaced start or stop condition programmable i 2 c address detection transfer problem detection end-of-byte transmission flag transmitter/receiver flag 10.5.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i 2 c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selection is made by software.
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 142/226 mode selection the interface can operate in the four following modes: slave transmitter/receiver master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, allowing then multi-master capability. communication flow in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of recognizing its own address (7 or 10-bit), and the general call address. the general call address detection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). the address is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to figure 69 . figure 69. i 2 c bus protocol acknowledge may be enabled and disabled by software. the i 2 c interface address and/or general call address can be selected by software. the speed of the i 2 c interface may be selected between standard (up to 100 khz) and fast i 2 c (up to 400 khz). sda/scl line control transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register. receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a programmable clock divider which depends on the i 2 c bus mode. scl sda 12 8 9 msb ack stop start condition condition
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 143/226 when the i 2 c cell is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistor used depends on the application. when the i 2 c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 70. i 2 c interface block diagram data register (dr) data shift register comparator own address register 1 (oar1) clock control register (ccr) status register 1 (sr1) control register (cr) control logic status register 2 (sr2) interrupt clock control data control scl or scli sda or sdai own address register 2 (oar2)
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 144/226 10.5.4 functional description refer to the cr, sr1 and sr2 registers in section 10.5.7 . for the bit definitions. by default the i 2 c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. first the interface frequency must be configured using the fri bits in the oar2 register. slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). note: in 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. header matched (10-bit mode only): the interface generates an acknowledge pulse if the ack bit is set. address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in sequence: ? acknowledge pulse if the ack bit is set. ? evf and adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register, holding the scl line low (see figure 71 transfer sequencing ev1). next, in 7-bit mode read the dr register to determine from the least significant bit (data direction bit) if the slave must enter receiver or transmitter mode. in 10-bit mode, after receiving the address sequence the slave is always in receive mode. it will enter transmit mode on rece iving a repeated start condit ion followed by the header sequence with matching address bits and the least significant bit set (11110xx1). slave receiver following the address reception and after sr1 register has been read, the slave receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: acknowledge pulse if the ack bit is set evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register followed by a read of the dr register, holding the scl line low (see figure 71 transfer sequencing ev2). slave transmitter following the address reception and after sr1 register has been read, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see figure 71 transfer sequencing ev3). when the acknowledge pulse is received the evf and btf bits are set by hardware with an interrupt if the ite bit is set.
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 145/226 closing slave communication after the last data byte is transferred a stop condition is generated by the master. the interface detects this condition and sets: evf and stopf bits with an interrupt if the ite bit is set. then the interface waits for a read of the sr2 register (see figure 71 transfer sequencing ev4). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop then the interface discards the data, released the lines and waits for another start condition. if it is a start then the interface discards the data and waits for the next slave address on the bus. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an interrupt if the ite bit is set. the af bit is cleared by reading the i2csr2 register. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a new interrupt. software must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. note: in both cases, scl line is not held low; howe ver, the sda line can remain low if the last bits transmitted are all 0. it is then necessary to release both lines by software. the scl line is not held low while af=1 but by other flags (sb or btf) that are set at the same time. how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte. smbus compatibility st7 i 2 c is compatible with smbus v1.1 protocol. it supports all smbus addressing modes, smbus bus protocols and crc-8 packet error checking. refer to an1713: smbus slave driver for st7 i 2 c peripheral.
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 146/226 master mode to switch from default slave mode to master mode a start condition generation is needed. start condition setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condition. once the start condition is sent, the evf and sb bits are set by hardware with an interrupt if the ite bit is set. the master then waits for a read of the sr1 register followed by a write in the dr register with the slave address, holding the scl line low (see figure 71 transfer sequencing ev5). slave address transmission 1. the slave address is then sent to the sda line via the internal shift register. ? in 7-bit addressing mode, one address byte is sent. ? in 10-bit addressing mode, sending the first byte including the header sequence causes the following event. the evf bit is set by hardware with interrupt generation if the ite bit is set. 2. the master then waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see figure 71 transfer sequencing ev9). 3. then the second address byte is sent by the interface. 4. after completion of this transfer (and acknowledge from the slave if the ack bit is set), the evf bit is set by hardware with interrupt generation if the ite bit is set. 5. the master waits for a read of the sr1 register followed by a write in the cr register (for example set pe bit), holding the scl line low (see figure 71 transfer sequencing ev6). 6. next the master must enter receiver or transmitter mode. note: in 10-bit addressing mode, to switch the master to receiver mode, software must generate a repeated start condition and resend the header sequence with the least significant bit set (11110xx1). master receiver following the address transmission and after sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: acknowledge pulse if the ack bit is set evf and btf bits are set by hardware with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register followed by a read of the dr register, holding the scl line low (see figure 71 transfer sequencing ev7). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte.
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 147/226 master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the internal shift register. the master waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see figure 71 transfer sequencing ev8). when the acknowledge bit is received, the interface sets evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrup t if ite is set. note that berr will not be set if an error is detected during the first pulse of each 9-bit transaction: single master mode if a start or stop is issued during the firs t pulse of a 9-bit transaction, the berr flag will not be set and transfer will c ontinue however the busy flag will be reset. to work around this, slave devices should issue a nack when they receive a misplaced start or stop. the reception of a nack or busy by the master in the middle of communication gives the possibility to reinitiate transmission. multimaster mode normally the berr bit would be set whenever unauthorized transmission takes place while transfer is already in progress. however, an issue will arise if an external master generates an unauthorized start or stop while the i 2 c master is on the first pulse of a 9-bit transaction. it is possible to work around this by polling the busy bit during i 2 c master mode transmission. the resetting of the busy bit can then be handled in a similar manner as the berr flag being set. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. the af bit is cleared by reading the i2csr2 register. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a new interrupt. software must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note: in all these cases, the scl lin e is not held low; however, the sda line can remain low if the last bits transmitted are all 0. it is then necessary to release both lines by software. the scl line is not held low while af=1 but by other flags (sb or btf) that are set at the same time.
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 148/226 figure 71. transfer sequencing 1. s=start, s r = repeated start, p=stop, a=acknowledge, na =non-acknowledge, evx=event (with interrupt if ite=1). 2. ev1: evf=1, adsl=1, cleared by reading sr1 register. 3. ev2: evf=1, btf=1, cleared by reading sr1 r egister followed by reading dr register. 4. ev3: evf=1, btf=1, cleared by reading sr1 r egister followed by writing dr register. 5. ev3-1: evf=1, af=1, btf=1; af is cleared by reading sr1 register. btf is cleared by releasing the lines (stop=1, stop=0) or by writing dr register (dr=ffh). if lines are released by stop=1, stop=0, the 7-bit slave receiver s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 7-bit slave transmitter s address a data1 a data2 a .... . data n na p ev1 ev3 ev3 ev3 ev3- 1 ev4 7-bit master receiver s address a data1 a data2 a .... . datan na p ev5 ev6 ev7 ev7 ev7 7-bit master transmitter s address a data1 a data2 a .... . data n ap ev5 ev6 ev8 ev8 ev8 ev8 10-bit slave receiver s header a address a data1 a ..... datan a p ev1 ev2 ev2 ev4 10-bit slave transmitter s r header a data1 a ... data n ap ev1 ev3 ev3 ev3- 1 ev4 10-bit master transmitter s header a address a data1 a .... datan a p ev5 ev9 ev6 ev8 ev8 ev8 10-bit master receiver s r header a data1 a ..... datan a p ev5 ev6 ev7 ev7
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 149/226 subsequent ev4 is not seen. 6. ev4: evf=1, stopf=1, cleared by reading sr2 register. 7. ev5: evf=1, sb=1, cleared by reading sr1 regi ster followed by writing dr register. 8. ev6: evf=1, cleared by reading sr1 register followed by writing cr register (for example pe=1). 9. ev7: evf=1, btf=1, cleared by reading sr1 r egister followed by reading dr register. 10. ev8: evf=1, btf=1, cleared by reading sr1 r egister followed by writing dr register. 11. ev9: evf=1, add10=1, cleared by reading sr1 r egister followed by writing dr register. 10.5.5 low power modes 10.5.6 interrupts figure 72. event flags and interrupt generation table 46. effect of low power modes on the i 2 c interface mode description wait no effect on i 2 c interface. i 2 c interrupts cause the device to exit from wait mode. halt i 2 c registers are frozen. in halt mode, the i 2 c interface is inactive and does not acknowledge data on the bus. the i 2 c interface resumes operation when the mcu is woken up by an interrupt with ?exit from halt mode? capability. table 47. description of interrupt events interrupt event (1) 1. the i 2 c interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable c ontrol bit is set and the i-bi t in the cc register is reset (rim instruction). event flag enable control bit exit from wait exit from halt 10-bit address sent event (master mode) add10 ite ye s n o end of byte transfer event btf yes no address matched event (slave mode) adsl yes no start bit generation event (master mode) sb yes no acknowledge failure event af yes no stop detection event (slave mode) stopf yes no arbitration lost event (multimaster configuration) arlo yes no bus error event berr yes no btf adsl sb af stopf arlo berr evf interrupt ite * * evf can also be set by ev6 or an error from the sr2 register. add10
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 150/226 10.5.7 register description i 2 c control register (i2ccr) reset value: 0000 0000 (00h) bits 7:6 = reserved. forced to 0 by hardware. bit 5 = pe peripheral enable bit this bit is set and cleared by software. 0: peripheral disabled 1: master/slave capability note: when pe=0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released while pe=0 when pe=1, the corresponding i/o pins are selected by hardware as alternate functions. to enable the i 2 c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4 = engc enable general call bit this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0). the 00h general call address is acknowledged (01h ignored). 0: general call disabled 1: general call enabled note: in accordance with the i 2 c standard, when gcal addressing is enabled, an i 2 c slave can only receive data. it will not transmit data to the master. bit 3 = start generation of a start condition bit . this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). in master mode: 0: no start generation 1: repeated start generation in slave mode: 0: no start generation 1: start generation when the bus is free bit 2 = ack acknowledge enable bit this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received 7 0 0 0 pe engc start ack stop ite read / write
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 151/226 bit 1 = stop generation of a stop condition bit this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe=0). in master mode: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. in slave mode: 0: no stop generation 1: release the scl and sda lines after the current byte transfer (btf=1). in this mode the stop bit has to be cleared by software. bit 0 = ite interrupt enable bit this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0: interrupts disabled 1: interrupts enabled refer to figure 72 for the relationship between the events and the interrupt. scl is held low when the add10, sb, btf or adsl flags or an ev6 event (see figure 71 ) is detected.
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 152/226 i 2 c status register 1 (i2csr1) reset value: 0000 0000 (00h) bit 7 = evf event flag this bit is set by hardware as soon as an event occurs. it is cleared by software reading sr2 register in case of error event or as described in figure 71 . it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: ? btf=1 (byte received or transmitted) ? adsl=1 (address matched in slave mode while ack=1) ? sb=1 (start condition generated in master mode) ? af=1 (no acknowledge received after byte transmission) ? stopf=1 (stop condition detected in slave mode) ? arlo=1 (arbitration lost in master mode) ? berr=1 (bus error, misplaced start or stop condition detected) ? add10=1 (master has sent header byte) ? address byte successfully tr ansmitted in master mode. bit 6 = add10 10-bit addressing in master mode this bit is set by hardware when the master has sent the first byte in 10-bit address mode. it is cleared by software reading sr2 register followed by a write in the dr register of the second address byte. it is also cleared by hardware when the peripheral is disabled (pe=0). 0: no add10 event occurred. 1: master has sent first address byte (header) bit 5 = tra transmitter/receiver bit when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after detection of stop condition (stopf=1), loss of bus arbitration (arlo=1) or when the interface is disabled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4 = busy bus busy bit this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. the busy flag of the i2csr1 register is cleared if a bus error occurs. 0: no communication on the bus 1: communication ongoing on the bus 7 0 evf add10 tra busy btf adsl m/sl sb read only
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 153/226 bit 3 = btf byte transfer finished bit this bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr register. it is also cleared by hardware when the interface is disabled (pe=0). ? following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev6 event (see figure 71 ). btf is cleared by reading sr1 register followed by writing the next byte in dr register. ? following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = adsl address matched bit (slave mode). this bit is set by hardware as soon as the received slave address matched with the oar register content or a general call is recognized. an interrupt is generated if ite=1. it is cleared by software reading sr1 register or by hardware when the interface is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched bit 1 = m/sl master/slave bit this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (pe=0). 0: slave mode 1: master mode bit 0 = sb start bit (master mode). this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading sr1 register followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disabled (pe=0). 0: no start condition 1: start condition generated
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 154/226 i 2 c status register 2 (i2csr2) reset value: 0000 0000 (00h) bits 7:5 = reserved. forced to 0 by hardware. bit 4 = af acknowledge failure bit this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low wh ile af=1 but by other flags (sb or btf) that are set at the same time. 0: no acknowledge failure 1: acknowledge failure bit 3 = stopf stop detection bit (slave mode) this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected bit 2 = arlo arbitration lost bit this bit is set by hardware when the interface loses the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). after an arlo event the interface switches back automatically to slave mode (m/sl=0). the scl line is not he ld low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected note: in a multimaster environment, when the interface is configured in master receive mode it does not perform arbitration during the reception of the acknowledge bit. mishandling of the arlo bit from the i2csr2 register may occur when a second master simultaneously requests the same data from the same slave and the i 2 c master does not acknowledge the data. the arlo bit is then left at 0 instead of being set. bit 1 = berr bus error bit this bit is set by hardware when the interface detects a misplaced start or stop condition. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition 7 0 0 0 0 af stopf arlo berr gcal read only
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 155/226 note: if a bus error occurs, a stop or a repeated start condition should be generated by the master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication bit 0 = gcal general call bit (slave mode). this bit is set by hardware when a general call address is detected on the bus while engc=1. it is cleared by hardware detecting a stop condition (stopf=1) or when the interface is disabled (pe=0). 0: no general call address detected on bus 1: general call address detected on bus i 2 c clock control register (i2cccr) reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i 2 c mode bit this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 0: standard i 2 c mode 1: fast i 2 c mode bits 6:0 = cc[6:0] 7-bit clock divider bits these bits select the speed of the bus (f scl ) depending on the i 2 c mode. they are not cleared when the interface is disabled (pe=0). refer to the electrical characteristics section for the table of values. note: the programmed f scl assumes no load on scl and sda lines. i 2 c data register (i2cdr) reset value: 0000 0000 (00h) bits 7:0 = d[7:0] 8-bit data register these bits contain the byte to be received or transmitted on the bus. ? transmitter mode: byte transmission start automatically when the software writes in the dr register. ? receiver mode: the first data byte is received automatically in the dr register using the least significant bit of the address. then, the following data bytes are received one by one after reading the dr register. 7 0 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 read / write 7 0 d7 d6 d5 d4 d3 d2 d1 d0 read / write
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 156/226 i 2 c own address register (i2coar1) reset value: 0000 0000 (00h) in 7-bit addressing mode bits 7:1 = add[7:1] interface address . these bits define the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe=0). bit 0 = add0 address direction bit. this bit is don?t care, the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe=0). note: address 01h is always ignored. in 10-bit addressing mode bits 7:0 = add[7:0] interface address . these are the least significant bits of the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe=0). i 2 c own address register (i2coar2) reset value: 0100 0000 (40h) bits 7:6 = fr[1:0] frequency bits these bits are set by software only when the interface is disabled (pe=0). to configure the interface to i 2 c specified delays select the value corresponding to the microcontroller frequency f cpu . bits 5:3 = reserved bits 2:1 = add[9:8] interface address these are the most significant bits of the i 2 c bus address of the interface (10-bit mode only). they are not cleared when the interface is disabled (pe=0). bit 0 = reserved. 7 0 add7 add6 add5 add4 add3 add2 add1 add0 read / write 7 0 fr1 fr0 0 0 0 add9 add8 0 read / write table 48. configuration of i 2 c delay times f cpu fr1 fr0 < 6 mhz 0 0 6 to 8 mhz 0 1
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 157/226 table 49. i 2 c register mapping and reset values address (hex.) register label 7654 3210 0064h i2ccr reset value 0 0 pe 0 engc 0 start 0 ack 0 stop 0 ite 0 0065h i2csr1 reset value evf 0 add10 0 tra 0 busy 0 btf 0 adsl 0 m/sl 0 sb 0 0066h i2csr2 reset value 0 0 0 af 0 stopf 0 arlo 0 berr 0 gcal 0 0067h i2cccr reset value fm/sm 0 cc6 0 cc5 0 cc4 0 cc3 0 cc2 0 cc1 0 cc0 0 0068h i2coar1 reset value add7 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 0069h i2coar2 reset value fr1 0 fr0 10 0 0 add9 0 add8 00 006ah i2cdr reset value msb 000 0 0 0 0 lsb 0
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 158/226 10.6 serial peripheral interface (spi) 10.6.1 introduction the serial peripheral interface (spi) allows full-duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 10.6.2 main features full duplex synchronous transfers (on three lines) simplex synchronous transfers (on two lines) master or slave operation 6 master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mo de fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 10.6.3 general description figure 73 on page 159 shows the serial peripheral interface (spi) block diagram. there are three registers: spi control register (spicr) spi control/status register (spicsr) spi data register (spidr) the spi is connected to external devices through four pins: miso: master in / slave out data mosi: master out / slave in data sck: serial clock out by spi masters and input by spi slaves ss : slave select: this input signal acts as a ?chip select? to let the spi master communicate with slaves individually and to avoid contention on the data lines. slave ss inputs can be driven by standard i/o ports on the master device.
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 159/226 figure 73. serial peripheral interface block diagram 10.6.4 functional description a basic example of interconnections between a single master and a single slave is illustrated in figure 74 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is always initiated by th e master. when the master device transmits data to a slave device via mosi pin, the sl ave device responds by sending data to the master device via the miso pin. this implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node (in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 77 on page 164 ) but master and slave must be programmed with the same timing mode. spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 160/226 figure 74. single master/ single slave application slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr register (see figure 76 ). in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 75 ): if cpha = 1 (data latched on second clock edge): ss internal must be held low during the entire transmission. this im plies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by managing the ss function by software (ssm = 1 and ssi = 0 in the spicsr register) if cpha = 0 (data latched on first clock edge): ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. if ss is not pulled high, a write collision error will occu r when the slave writes to the shift register (see section : write collision error (wcol) ). 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 161/226 figure 75. generic ss timing diagram figure 76. hardware/software slave select management master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). how to operate the spi in master mode to operate the spi in master mode, perform the following steps in order: 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 77 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note: mstr and spe bits re main set only if ss is high). caution: if the spicsr register is not wr itten first, the spicr register setting (mstr bit) may be not taken into account. the transmit sequence begins when software writes a byte in the spidr register. byte 1 byte 2 byte 3 mosi/miso master ss slave ss (if cpha = 0) slave ss (if cpha = 1) 1 0 ss internal ssm bit ssi bit ss external pin
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 162/226 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: the spif bit is set by hardware. an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the following actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 77 ). note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in section : slave select management and figure 75 . if cpha = 1 ss must be held low continuously. if cpha = 0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and se t the spe bit to enable the spi i/o functions. slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its mosi pin. when data transfer is complete: the spif bit is set by hardware. an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a write or a read to the spidr register note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read.
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 163/226 the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section : overrun condition (ovr) ). 10.6.5 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 77 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge. figure 77 shows an spi transfer with the four combinations of the cpha and cpol bits. the diagram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin and the mosi pin are directly connected between the master and the slave device. note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit.
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 164/226 figure 77. data clock timing diagram 10.6.6 error flags master mode fault (modf) master mode fault occurs when the master device?s ss pin is pulled low. when a master mode fault occurs: the modf bit is set and an spi interrupt request is generated if the spie bit is set. the spe bit is reset. this blocks all output from the device and disables the spi peripheral. the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha = 1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3bit 2bit 1lsbit miso (from master) mosi ss (to slave) capture strobe cpha = 0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0)
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 165/226 1. a read access to the spicsr regi ster while the modf bit is set. 2. a write to the spicr register. note: to avoid any conflicts in an ap plication with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their original state during or after this clearing sequence. hardware does not allow the us er to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multimaster configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multimaster conflict and allows software to handle this using an interrupt routine and either perform a reset or return to an application default state. overrun condition (ovr) an overrun condition occurs when the master device has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. write collision error (wcol) a write collision occurs when the software trie s to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted and the softwa re write will be unsuccessful. write collisions can occur both in master and slave mode. see also section : slave select management . note: a "read collision" will never occu r since the received data byte is placed in a buffer in which access is always synchronous with the cpu operation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 78 ).
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 166/226 figure 78. clearing the wcol bit (write collision flag) software sequence single master and multimaster configurations there are two types of spi systems: single master system multimaster system single master system a typical single master system may be configured using a device as the master and four devices as slaves (see figure 79 ). the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line, the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are connected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with command fields. multimaster system a multimaster system may also be configured by the user. transfer of master control could be implemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multimaster system is principally handled by the mstr bit in the spicr register and the modf bit in the spicsr register. clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif = 0 wcol = 0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol = 0 read spicsr read spidr note: writing to the spidr register instead of reading it does not reset the wcol bit result result
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 167/226 figure 79. single master / multiple slave configuration 10.6.7 low power modes 10.6.8 interrupts note: the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave device slave device slave device slave device master device table 50. low power mode descriptions mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the device is woken up by an interrupt with ?exit from halt mode? capability. the data received is subsequently read from th e spidr register when the software is running (interrupt vector fetching). if several data are received before the wakeup event, then an overrun error is generated. this error can be detected after the fetch of the interrupt r outine that woke up the device. table 51. interrupt events interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes no master mode fault event modf no overrun error ovr
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 168/226 10.6.9 register description spi control register (spicr) reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever an end of transfer event, master mode fault or overrun error occurs (spif = 1, modf = 1 or ovr = 1 in the spicsr register) bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section : master mode fault (modf) ). the spe bit is cleared by reset, so the spi peripheral is not initially connected to the external pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable . this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 52: spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled this bit has no effect in slave mode. bit 4 = mstr master mode. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section : master mode fault (modf) ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit determines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit. 7 0 spie spe spr2 mstr cpol cpha spr1 spr0 read / write
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 169/226 bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency. these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. these 2 bits have no effect in slave mode. table 52. spi master mode sck frequency serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 170/226 spi control/status register (spicsr) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only) . this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie = 1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an external device has been completed. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. bit 6 = wcol write collision status (read only) . this bit is set by hardware when a write to the spidr register is done during a transmit sequence. it is cleared by a software sequence (see figure 75). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr spi overrun error (read only) . this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section overrun condition (ovr)). an interrupt is generated if spie = 1 in the spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only) . this bit is set by hardware when the ss pin is pulled low in master mode (see section master mode fault (modf)). an spi interrupt can be generated if spie = 1 in the spicr register. this bit is cleared by a software sequence (an access to the spicsr register while modf = 1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable . this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe = 1) 1: spi output disabled 7 0 spif wcol ovr modf - sod ssm ssi read / write (some bits read only)
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 171/226 bit 1 = ssm ss management . this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section slave select management. 0: hardware management (ss managed by external pin) 1: software management (internal ss signal controlled by ssi bit. external ss pin free for general-purpose i/o) bit 0 = ssi ss internal mode . this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0: slave selected 1: slave deselected spi data i/o register (spidr) reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register will initia te transmission/recepti on of another byte. note: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value located in the buffer and not the content of the shift register (see figure 73 ). 7 0 d7 d6 d5 d4 d3 d2 d1 d0 read / write
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 172/226 table 53. spi register map and reset values address (hex.) register label 76543210 70 spidr reset value msb xxxxxxx lsb x 71 spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 72 spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 173/226 10.7 10-bit a/d converter (adc) 10.7.1 introduction the on-chip analog to digital converter (adc) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. this peripheral has up to 10 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 10 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 10.7.2 main features 10-bit conversion up to 10 channels with multiplexed input linear successive approximation data register (dr) whic h contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 80 . 10.7.3 functional description analog power supply v dda and v ssa are the high and low level reference voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines.
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 174/226 figure 80. adc block diagram digital a/d conversion result the conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v dda (high-level voltage reference) then the conversion result is ffh in the adcdrh register and 03h in the adcdrl register (without overflow indication). if the input voltage (v ain ) is lower than v ssa (low-level voltage reference) then the conversion result in the adcdrh an d adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conv ersion is stored in the adcdrh and adcdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and samp ling not being completed in the alloted time. ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 4 d1 d0 adcdrl 00 0 slow r adc c adc hold control f adc f cpu 0 1 1 0 div 2 div 4 slow bit 00 ch3
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 175/226 configuring the a/d conversion the analog input ports must be configured as input, no pull-up, no interrupt (see section 9: i/o ports ). using these pins as analog inputs does not affe ct the ability of the port to be read as a logic input. to assign the analog channel to convert, sele ct the ch[2:0] bits in the adccsr register. set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: the eoc bit is set by hardware. the result is in the adcdr registers. a read to the adcdrh or a write to any bit of the adccsr register resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll the eoc bit 2. read adcdrl 3. read adcdrh. this cl ears eoc automatically. to read only 8 bits, perform the following steps: 1. poll eoc bit 2. read adcdrh. this cl ears eoc automatically. changing the conversion channel the application can change channels during conversion. when software modifies the ch[3:0] bits in the adccsr register, the cu rrent conversion is stopped, the eoc bit is cleared, and the a/d converter starts converting the newly selected channel. 10.7.4 low power modes the a/d converter may be disabled by resetting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. 10.7.5 interrupts none. table 54. effect of low power modes on the a/d converter mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time t stab (see electrical characteristics) before accurate conversions can be performed.
on-chip peripherals st7foxf1, ST7FOXK1, st7foxk2 176/226 10.7.6 register description control/status register (adccsr) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion bit this bit is set by hardware. it is cleared by hardware when software reads the adcdrh register or writes to any bit of the adccsr register. 0: conversion is not complete 1: conversion complete bit 6 = speed adc clock selection bit this bit is set and cleared by software. it is used together with the slow bit to configure the adc clock speed. refer to the table in the slow bit description (adcdrl register). bit 5 = adon a/d converter on bit this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bit 4 = reserved , must be kept cleared. bits 3:0 = ch[3:0] channel selection these bits select the analog input to convert. they are set and cleared by software. 7 0 eoc speed adon 0 ch3 ch2 ch1 ch0 read only read/write table 55. channel selection using ch[3:0] channel pin (1) 1. the number of channels is device dependen t. refer to the devic e pinout description. ch3 ch2 ch1 ch0 ain0 0 0 0 0 ain1 0 0 0 1 ain2 0 0 1 0 ain3 0 0 1 1 ain4 0 1 0 0 ain5 0 1 0 1 ain6 0 1 1 0 ain7 0 1 1 1 ain8 1 0 0 0 ain9 1 0 0 1
st7foxf1, ST7FOXK1, st7foxk2 on-chip peripherals 177/226 data register high (adcdrh) reset value: xxxx xxxx (xxh) bits 7:0 = d[9:2] msb of analog converted value adc control/data register low (adcdrl) reset value: 0000 00xx (0xh) bits 7:4 = reserved. forced by hardware to 0. bit 3 = slow slow mode bit this bit is set and cleared by software. it is used toge ther with the speed bit in the adccsr register to configure the adc cl ock speed as shown on the table below. bit 2 = reserved. forced by hardware to 0. bits 1:0 = d[1:0] lsb of analog converted value 7 0 d9 d8 d7 d6 d5 d4 d3 d2 read only 7 0 0000slow0d1d0 read/write table 56. configuring the adc clock speed f adc (1) 1. the maximum allowed value of f adc is 4 mhz (see section 12.11 on page 209 ) slow speed f cpu /2 0 0 f cpu 01 f cpu /4 1 x table 57. adc register mapping and reset values address (hex.) register label 765 4 3 2 10 0036h adccsr reset value eoc 0 speed 0 adon 0 0 0 ch3 0 ch2 0 ch1 0 ch0 0 0037h adcdrh reset value d9 x d8 x d7 x d6 x d5 x d4 x d3 x d2 x 0038h adcdrl reset value 0 0 0 0 0 0 0 slow 0 0 d1 x d0 x
instruction set st7foxf1, ST7FOXK1, st7foxk2 178/226 11 instruction set 11.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in seven main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdivided in two submodes called long and short: long addressing mode is more powerful because it can use the full 64 kbyte address space, however it uses more bytes and more cpu cycles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory instructions use shor t addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 58. description of addressing modes addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 table 59. st7 addressing mode overview mode syntax destination/ source pointer address pointer size length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2
st7foxf1, ST7FOXK1, st7foxk2 instruction set 179/226 11.1.1 inherent mode all inherent instructions consist of a single byte. the opcode fully specifies all the required information for the cpu to process the operation. long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc- 128/pc+127 (1) + 1 relative indirect jrne [$10] pc- 128/pc+127 (1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 1. at the time the instruction is executed, the program counter (pc) points to the instruction following jrxx. table 59. st7 addressing mode overview (continued) mode syntax destination/ source pointer address pointer size length (bytes) table 60. instructions supporting inherent addressing mode instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret subroutine return iret interrupt su broutine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement
instruction set st7foxf1, ST7FOXK1, st7foxk2 180/226 11.1.2 immediate mode immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. imm 11.1.3 direct modes in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two submodes: direct (short) addressing mode the address is a byte, thus requires only 1 by te after the opcode, but only allows 00 - ff addressing space. direct (long) addressing mode the address is a word, thus allowing 64 kbyte addressing space, but requires 2 bytes after the opcode. 11.1.4 indexed modes (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three submodes: indexed mode (no offset) there is no offset (no extra byte after the opcode), and allows 00 - ff addressing space. indexed mode (short) the offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1fe addressing space. mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles table 60. instructions supporting inherent addressing mode (continued) instruction function table 61. instructions supporting inherent immediate addressing mode immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
st7foxf1, ST7FOXK1, st7foxk2 instruction set 181/226 indexed mode (long) the offset is a word, thus allowing 64 kbyte addressing space and requires 2 bytes after the opcode. 11.1.5 indirect modes (short, long) the required data byte to do the operation is found by its memory address, located in memory (pointer). the pointer address follows the opcode. the indirect addressing mode consists of two submodes: indirect mode (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect mode (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. 11.1.6 indirect indexed modes (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (x or y) with a pointer value located in memory. the pointer address follows the opcode. the indirect indexed addressing mode consists of two submodes: indirect indexed mode (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed mode (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 62. instructions supporting direct, i ndexed, indirect and indirect indexed addressing modes instructions function long and short instructions ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtraction operations bcp bit compare
instruction set st7foxf1, ST7FOXK1, st7foxk2 182/226 11.1.7 relative modes (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two submodes: relative mode (direct) the offset follows the opcode. relative mode (indirect) the offset is defined in memory, of which the address follows the opcode. short instructions only clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine table 62. instructions supporting direct, i ndexed, indirect and indirect indexed addressing modes (continued) instructions function table 63. instructions supporting relative modes available relative direct/i ndirect instructions function jrxx conditional jump callr call relative
st7foxf1, ST7FOXK1, st7foxk2 instruction set 183/226 11.2 instruction groups the st7 family devices use an instruction set co nsisting of 63 instruct ions. the instructions may be subdivided into 13 main groups as illustra ted in the following table: using a prebyte the instructions are described with 1 to 4 bytes. in order to extend the number of available opcodes for an 8-bit cpu (256 opcodes), three different prebyte opcodes are defined. these prebytes modify the meaning of the instruction they precede. the whole instruction becomes by: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruction using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. table 64. st7 instruction set load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotate sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf
instruction set st7foxf1, ST7FOXK1, st7foxk2 184/226 11.2.1 illegal opcode reset in order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detecti on is implemented: a reset is g enerated if the code to be executed does not correspond to any opcode or prebyte value. this, combined with the watchdog, allows the detection and recovery from an unexpected fault or interference. a valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset. i table 65. illegal opcode detection mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ?
st7foxf1, ST7FOXK1, st7foxk2 instruction set 185/226 jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7.. 4]<=>dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 table 65. illegal opcode detection (continued) mnemo description function/example dst src h i n z c
instruction set st7foxf1, ST7FOXK1, st7foxk2 186/226 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z table 65. illegal opcode detection (continued) mnemo description function/example dst src h i n z c
st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 187/226 12 electrical characteristics 12.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 12.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 12.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5 v (for the 4.5 v v dd 5.5 v voltage range). they are given only as design guidelines and are not tested. 12.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 81 . figure 81. pin loading conditions 12.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 82 . c l st7 pin
electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 188/226 figure 82. pin input voltage 12.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in st7 pin table 66. voltage characteristics symbol ratings maximum value unit v dd - v ss supply voltage 7.0 v v in input voltage on any pin (1)(2) 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operat ion, this connection has to be done through a pull- up or pull-down resistor (typical: 4.7 k ? for reset , 10 k ? for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 189/226 table 67. current characteristics symbol ratings maximum value unit i vdd total current into v dd power lines (source) (1) 1. all power (v dd ) and ground (v ss ) lines must always be connect ed to the external supply. 75 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any standard i/o and control pin 20 output current sunk by any high sink i/o pin 40 output current source by any i/os and control pin - 25 i inj(pin) (2)(3) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 190/226 12.3 operating conditions 12.3.1 general operating conditions t a = -40 to +85 c unless otherwise specified. 12.3.2 operating conditions with low voltage detector (lvd) t a = -40 to 85 c unless otherwise specified. , table 69. general operating conditions symbol parameter conditions min max unit v dd supply voltage f cpu = 8 mhz max. 4.5 5.5 v f cpu cpu clock frequency 4.5 v v dd 5.5 v up to 8 mhz table 70. operating characteristics with lvd symbol parameter conditions min typ max unit v it+ (lvd) reset release threshold (v dd rise) 3.9 4.2 4.5 v v it- (lvd) reset generation threshold (v dd fall) 3.7 4.0 4.3 v hys lvd voltage threshold hysteresis v it+ (lvd) -v it- (lvd) 150 mv v tpor v dd rise time rate (1)(2) 1. not tested in production. the v dd rise time rate condition is needed to ensure a correct device power-on and lvd reset release. when the v dd slope is outside these values, the lvd may not release properly the reset of the mcu. 2. use of lvd with capacitive power supply: with this type of power s upply, if power cuts occur in the application, it is recommended to pull v dd down to 0 v to ensure optimum restart conditions. refer to circuit example in figure 89 on page 207 . 2 s/v i dd(lvd) lvd current consumption v dd = 5 v 80 140 a
st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 191/226 12.3.3 internal rc oscillator to improve clock stability and frequency accura cy, it is recommended to place a decoupling capacitor, typically 100 nf, between the v dd and v ss pins as close as possible to the st7 device internal rc oscillator calibrated at 5.0 v the st7 internal clock can be supplied by an internal rc oscillator (selectable by option byte). table 71. internal rc oscillator characteristics (5.0 v calibration) symbol parameter conditions min typ max unit f rc internal rc oscillator frequency rccr = ff (reset value), t a = 25 c, v dd = 5 v 5.5 mhz rccr=rccr0 (1) , t a = 25 c, v dd = 5 v 1. see section 6.1.1: internal rc oscillator 8 f g(rc) rc trimming granularity t a = 25 c, v dd = 5 v 6 khz acc rc accuracy of internal rc oscillator with rccr=rccr0 1) t a = 25 c, v dd = 5 v (2) without user calibration 7 % t a = 25 c, v dd = 4.5 to 5.5 v (2) with user calibration -2 2 % t a = 0 to +85 c, v dd = 4.5 to 5.5 v (2) with user calibration 2. guaranteed by characterization -2.5 4 % t a = -40 to 0 c, v dd = 4.5 to 5.5 v (2) with user calibration -4 2.5 % t su(rc) rc oscillator setup time t a = 25 c, v dd = 5 v 4 (3) 3. not tested in production s
electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 192/226 12.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consumption, the two current values must be added (except for halt mode for which the clock is stopped). 12.4.1 supply current t a = -40 to +85 c unless otherwise specified. table 72. supply current characteristics symbol parameter conditions typ max unit i dd supply current in run mode (1) v dd =5v f cpu = 4 mhz 2.5 4.5 (2) ma f cpu = 8 mhz 5.0 9 supply current in wait mode (3) f cpu = 4 mhz 1.1 2 (2) f cpu = 8 mhz 2 3.5 supply current in slow mode (4) f cpu /32 = 250 khz 550 950 a supply current in slow-wait mode (5) f cpu /32 = 250 khz 450 750 supply current in awufh mode (6)(7) 50 100 (2) supply current in active halt mode 120 250 supply current in halt mode (8) t a = 85 c 0.5 5 1. cpu running with memory access , all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 2. data based on characterization, not tested in production. 3. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in re set state; clock input (clkin) driven by external sq uare wave, lvd disabled. 4. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) dr iven by external square wave, lvd disabled. 5. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pi ns in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 6. all i/o pins in input mode with a static value at v dd or v ss (no load). data tested in production at v dd max. and f cpu max. 7. this consumption refers to the halt period only an d not the associated run period which is software dependent. 8. all i/o pins in output mode with a static value at v ss (no load), lvd disabled. data based on characterization results, tested in production at v dd max and f cpu max.
st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 193/226 12.4.2 on-chip peripherals table 73. on-chip peripheral characteristics symbol parameter conditions typ unit i dd(spi) spi supply current (1) 1. data based on a differential i dd measurement between reset configuration and a permanent spi master communication (data sent equal to 55h). f cpu =8 mhz v dd = 5.0 v 200 a i dd(at) 12-bit auto-reload timer supply current (2) 2. data based on a differential i dd measurement between reset confi guration (timer stopped) and a timer running in pwm mode at f cpu = 8 mhz. f cpu =8 mhz v dd = 5.0 v 50 a i dd(i2c) i 2 c supply current (3) 3. data based on a differential i dd measurement between reset configuration (i 2 c disabled) and a permanent i 2 c master communication at 100 khz (data sent equal to 55h). this measurement include the pad toggling consumption (4.7 kohm exter nal pull-up on clock and data lines). f cpu =8 mhz v dd = 5.0 v 1000 a i dd(adc) adc supply current when converting (4) 4. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. f adc =4 mhz v dd = 5.0 v 600 a
electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 194/226 12.5 communication interface characteristics 12.5.1 i 2 c interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (sdai and scli). the st7 i 2 c interface meets the electrical and timing requirements of the standard i 2 c communication protocol. t a = -40c to 85 c, unless otherwise specified. table 102 gives the values to be written in the i2cccr register to obtain the required i 2 c scl line frequency. table 74. i 2 c interface characteristics symbol parameter conditions min max unit f scl (1) 1. the i 2 c interface will not function below the minimum clock speed of 4 mhz (see ta bl e 7 5 ). i2c scl frequency f cpu =4 mhz to 8 mhz, v dd = 4.5 to 5.5 v 400 khz table 75. scl frequency (multimaster i 2 c interface) (1)(2)(3) f scl i2cccr value f cpu = 4 mhz, v dd = 5 v f cpu = 8 mhz, v dd = 5 v r p =3.3k ? r p =4.7k ? r p =3.3k ? r p =4.7k ? 400 na na 84h 84h 300 na na 86h 86h 200 84h 84h 8ah 8ah 100 11h 11h 25h 24h 50 25h 25h 4dh 4ch 20 61h 62h ffh ffh 1. r p = external pull-up resistance, f scl = i 2 c speed. 2. for fast mode speeds, achieved speed can have 5% tolerance. for other speed ranges, achieved speed can have 2% tolerance. 3. the above variations depend on the accuracy of the external components used.
st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 195/226 12.5.2 spi interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). table 76. spi interface characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) (1) 1. data based on design simulation, not tested in production. ss setup time (2) 2. depends on f cpu . for example, if f cpu =8 mhz, then t cpu = 1/f cpu =125 ns and t su(ss ) =550 ns slave (4 x t cpu ) + 50 ns t h(ss ) (1) ss hold time slave 120 t w(sckh) (1) t w(sckl) (1) sck high and low time master slave 100 90 t su(mi) (1) t su(si) (1) data input setup time master slave 100 100 t h(mi) (1) t h(si) (1) data input hold time master slave 100 100 t a(so) (1) data output access time slave 0 120 t dis(so) (1) data output disable time slave 240 t v(so) (1) data output valid time slave (after enable edge) 120 t h(so) (1) data output hold time 0 t v(mo) (1) data output valid time master (after enable edge) 120 t h(mo) (1) data output hold time 0
electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 196/226 figure 83. spi slave timing diagram with cpha=0 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, t he pin status depends on the i/o port configuration. figure 84. spi slave timing diagram with cpha=1 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, t he pin status depends on the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out see note 2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in ss input sck input cpha=1 mosi input miso output cpha=1 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in
st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 197/226 figure 85. spi master timing diagram 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, the pin status depends of the i/o port configuration. 12.6 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . ss input sck input cpha = 0 mosi output miso input cpha = 0 cpha = 1 cpha = 1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 seenote2 cpol = 0 cpol = 1 cpol = 0 cpol = 1 t r(sck) t f(sck) t h(mo) t v(mo) table 77. general timings symbol parameter (1) 1. guaranteed by design. not tested in production. conditions min typ (2) 2. data based on typical application software. max unit t c(inst) instruction cycle time f cpu = 8 mhz 2312t cpu 250 375 1500 ns t v(it) interrupt reaction time (3) t v(it) = ? t c(inst) + 10 3. time measured between interrupt event and interrupt vector fetch. ? t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. f cpu = 8 mhz 10 22 t cpu 1.25 2.75 s
electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 198/226 figure 86. typical application with an external clock source 12.6.1 auto wakeup from halt oscillator (awu) table 78. external clock source characteristics symbol parameter conditions min typ max unit v osc1h or v clkin_h osc1/clkin input pin high level voltage see figure 86 0.7xv dd v dd v v osc1l or v clkin_l osc1/clkin input pin low level voltage v ss 0.3xv dd t w(osc1h) or t w(clkinh) t w(osc1l) or t w(clkinl) osc1/clkin high or low time (1) 1. data based on design simulation and/or technology characteristics, not tested in production. 15 ns t r(osc1) or t r(clkin) t f(osc1) or t f(clkin) osc1/clkin rise or fall time (1) 15 i l oscx/clkin input leakage current v ss v in v dd 1 a osc1/clkin osc2 f osc external st7xxx clock source not connected internally v osc1l or v clkinl v osc1h or v clkinh t r(osc1 or clkin)) t f(osc1 or clkin) t w(osc1h or clkinh)) t w(osc1l or clkinl) i l 90% 10% table 79. awu from halt characteristics symbol parameter (1) 1. guaranteed by design. not tested in production. conditions min typ max unit f awu awu oscillator frequency 16 32 64 khz t rcsrt awu oscillator startup time 50 s
st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 199/226 12.6.2 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with ten different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possibl e to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to t he crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). figure 87. typical application with a crystal or ceramic resonator table 80. crystal/ceramic resonator oscillator characteristics symbol parameter conditions min typ max unit f crosc crystal oscillator frequency 2 16 mhz c l1 c l2 recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (r s ) tbd pf osc2 osc1 f osc c l1 c l2 i 2 resonator when resonator with integrated capacitors r d st7fox
electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 200/226 12.7 memory characteristics t a = -40 c to 85 c, unless otherwise specified. table 81. ram and hardware registers characteristics symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers ( only in halt mode). guaranteed by c onstruction, not tested in production. halt mode (or reset) 1.6 v table 82. flash program memory characteristics symbol parameter conditions min typ max unit v dd operating voltage for flash write/erase refer to operating range of v dd with t a, section 12.3.1 on page 190 4.5 5.5 v t prog programming time for 1~32 bytes (1) 1. up to 32 bytes can be programmed at a time. t a =? 40 to +85 c 5 10 ms programming time for 4 kbytes t a = +25 c 0.64 1.28 s t ret data retention (2) 2. data based on reliability test results and monitored in production. t a = +55 c (3) 3. the data retention time increases when the t a decreases. 20 years n rw write erase cycles t a = +25 c 1k cycles i dd supply current (4) 4. guaranteed by design. not tested in production. read / write / erase modes f cpu = 8 mhz, v dd = 5.5 v 2.6 ma no read/no write mode 100 a power down mode / halt 00.1 a
st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 201/226 12.8 emc (electromagnetic co mpatibility) characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 12.8.1 functional ems (elect romagnetic susceptibility) based on a simple running application on the product (toggling two leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually fo rcing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 83. ems test results symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-2 2b v fftb fast transient voltage burst limits to be applied through 100pf on v dd and v ss pins to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-4 3b
electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 202/226 12.8.2 emi (electro magnetic interference) based on a simple application running on the product (toggling two leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the boar d and the loading of each pin. table 84. emi emissions symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 8/4mhz 16/8mhz s emi peak level v dd = 5 v, t a = +25 c, conforming to sae j 1752/3 0.1 mhz to 30 mhz 28 32 db v 30 mhz to 130 mhz 31 34 130 mhz to 1 ghz 18 26 sae emi level 3 3.5 -
st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 203/226 12.8.3 absolute maximum rati ngs (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. for more details, refer to the application note an1181. static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance. a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. table 85. esd absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 4000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c 500 table 86. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +85 c a
electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 204/226 12.9 i/o port pin characteristics 12.9.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 88. two typical applications with unused i/o pin 1. during normal operation the iccclk pin must be pulled-up, internally or externally (external pull-up of 10k mandatory in noisy environment). this is to av oid entering icc mode unexpectedly during a reset. 2. i/o can be left unconnected if it is configured as output (0 or 1) by the software. this has the advantage of greater emc robustness and lower cost. table 87. general characteristics symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3v dd v v ih input high level voltage 0.7v dd v dd +0.3 v hys schmitt trigger voltage hysteresis (1) 400 mv i l input leakage current v ss v in v dd 1 a i s static current consumption induced by each floating input pin (2) floating input mode 400 r pu weak pull-up equivalent resistor (3) v in = v ss v dd =5 v 100 120 140 k ? c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time (1) c l = 50 pf between 10% and 90% 25 ns t r(io)out output low to high level rise time (1) 25 t w(it)in external interrupt pulse time (4) 1t cpu 1. data based on validation/design results. 2. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull- up or pull-down resistor (see figure 88 ). static peak current value taken at a fixed v in value, based on design simulation and technology characteristics, not tested in pr oduction. this value depends on v dd and temperature values. 3. the r pu pull-up equivalent resistor is based on a resistive transistor. 4. to generate an external interrupt, a mini mum pulse width has to be applied on an i/o port pin configured as an external interrupt source. 10k ? unused i/o port st7xxx 10k ? unused i/o port st7xxx v dd
st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 205/226 12.9.2 output driving current subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. table 88. output driving current characteristics symbol parameter conditions min max unit v ol (1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time v dd = 5 v i io =+5 ma, t a 85c 1.0 v i io =+2ma, t a 85c 0.4 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time i io =+20ma,t a 85c 1.3 i io =+8mat a 85c 0.75 v oh (2) output high level voltage for an i/o pin when 4 pins are sourced at same time i io =-5ma,t a 85c v dd -1.5 i io =-2mat a 85c v dd -0.8 1. the i io current sunk must always respect the absolute maximum rating specified in section table 67. and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect t he absolute maximum rating specified in section table 67. and the sum of i io (i/o ports and control pins) must not exceed i vdd .
electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 206/226 12.10 control pin characteristics 12.10.1 asynchronous reset pin t a = -40 to 85 c, unless otherwise specified. table 89. asynchronous reset pin characteristics symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3v dd v v ih input high level voltage 0.7v dd v dd +0.3 v hys schmitt trigger voltage hysteresis (1) 2v v ol output low level voltage (2) v dd = 5 v i io = +2 ma 200 mv r on pull-up equivalent resistor (3) v in = v ss v dd = 5 v 30 50 70 k ? t w(rstl)out generated reset pulse duration internal reset sources 90 (1) s t h(rstl)in external reset pulse hold time (4) 20 s t g(rstl)in filtered glitch duration 200 ns 1. data based on characterization results, not tested in production 2. the i io current sunk must always respect t he absolute maximum rating specified in section table 67. on page 189 and the sum of i io (i/o ports and control pins) must not exceed i vss . 3. the r on pull-up equivalent resistor is based on a resi stive transistor. specified for voltages on reset pin between v ilmax and v dd 4. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored.
st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 207/226 figure 89. reset pin protection when lvd is enabled 1. the reset network protects the device against parasitic resets. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). whatev er the reset source is (i nternal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 12.10.1 on page 206 . otherwise the reset will not be taken into account internally. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin is less than the absolut e maximum value specified for i inj(reset) in section table 67. on page 189 . 2. when the lvd is enabled, it is recommended not to c onnect a pull-up resistor or capacitor. a 10nf pull- down capacitor is required to filter noise on the reset line. 3. in case a capacitive power supply is used, it is recommended to connect a 1m ? pull-down resistor to the reset pin to discharge any residual voltage i nduced by the capacitive effect of the power supply (this will add 5a to the power consumption of the mcu). tips when using the lvd check that all recommendations related to iccclk and reset circuit have been applied (see caution in table 2 on page 16 and notes above). check that the power supply is properly decoupled (100nf + 10f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100nf + 1m ? pull-down on the reset pin. the capacitors connected on the reset pin and also the power supply are key to avoid any start-up marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. othe rwise: replace 10nf pull-down on the reset pin with a 5f to 20f capacitor.? 0.01 f st7xxx pulse generator filter r on v dd internal reset reset external required 1m ? optional (note 3) watchdog lvd reset illegal opcode
electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 208/226 figure 90. reset pin protection when lvd is disabled 1. the reset network protects t he device against par asitic resets. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). whatever the reset source is (int ernal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 12.10.1 on page 206 . otherwise the reset will not be taken into account internally. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section table 67. on page 189 . 2. please refer to section 11.2.1 on page 184 for more details on ill egal opcode reset conditions. 0.01 f external reset circuit user required st7xxx pulse generator filter r on v dd internal reset watchdog illegal opcode
st7foxf1, ST7FOXK1, st7foxk2 electrical characteristics 209/226 12.11 10-bit adc characteristics subject to general operating condition for v dd , f osc , and t a unless otherwise specified. figure 91. typical application with adc table 90. adc characteristics symbol parameter conditions min typ (1) max unit f adc adc clock frequency 4 mhz v ain conversion voltage range v ssa v dda v r ain external input resistor v dd = 5 v, f adc = 4 mhz 8k (2) ? 4.5 v v dd 5.5 v, f adc = 2 mhz 10k (2) c adc internal sample and hold capacitor 6pf t stab stabilization time after adc enable f cpu = 8 mhz, f adc = 4 mhz 0 (3) s t adc conversion time (sample+hold) 3.5 - sample capacitor loading time - hold conversion time 4 10 1/f adc 1. unless otherwise specified, typical data are based on t a = 25 c and v dd -v ss = 5 v. they are given only as design guidelines and are not tested. 2. any added external serial resistor wi ll downgrade the adc accuracy (especially for resistance greater than the maximum value). data guaranteed by design, not tested in production. 3. the stabilization time of the a/d converter is masked by the first t load . the first conversion after the enable is then always valid. ainx st7xxx v dd i l 1 a v t 0.6 v v t 0.6 v c adc v ain r ain 10-bit a/d conversion
electrical characteristics st7foxf1, ST7FOXK1, st7foxk2 210/226 figure 92. adc accura cy characteristics table 91. adc accuracy with v dd = 4.5 to 5.5 v symbol (1) 1. data based on characterization results over the whole temperature range. parameter conditions typ max unit |e t | total unadjusted error f cpu =8 mhz, f adc =4 mhz (1) 2.0 5.0 lsb |e o | offset error 0.9 2.5 |e g | gain error 1.0 1.5 |e d | differential linearity error 1.2 3.5 |e l | integral linearity error 1.1 4.5 e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line et=total unadjusted error: maximum deviation between the actual and the ideal transfer curves. eo=offset error: deviation between the first actual transition and the first ideal one. eg=gain error: deviation between the last ideal transition and the last actual one. ed=differential linearity error: maximum deviation between actual steps and the ideal one. el=integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dd v ss
st7foxf1, ST7FOXK1, st7foxk2 device configuration and ordering information 211/226 13 device configuration and ordering information this device is available for production in user programmable version (flash). st7fox xflash devices are shipped to customers with a default program memory content (ffh). 13.1 option bytes the two option bytes allow the hardware configuration of the microcontroller to be selected. the option bytes can be accessed only in programming mode (for example using a standard st7 programming tool). 13.1.1 option byte 1 bits 7:6 = cksel[1:0] start-up clock selection. these bits are used to select the startup frequency. by default, the internal rc is selected. bits 5:3 = reserved, must always be 1. bit 2 = lv d low voltage detection selection. this option bit enables the low voltage detection block (lvd). 0: lvd on 1: lvd off (default value) bit 1 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) bit 0 = wdg halt watchdog reset on halt this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode table 92. startup clock selection configuration cksel1 cksel0 internal rc as startup clock 0 0 awu rc as a startup clock 0 1 external crystal/ceramic resonator 1 0 external clock 1 1
device configuration and ordering information st7foxf1, ST7FOXK1, st7foxk2 212/226 13.1.2 option byte 0 opt 7 = awuck auto wake up clock selection 0: 32-khz oscillator (vlp) selected as awu clock 1: awu rc oscillator selected as awu clock. note: if this bit is reset, oscrange[2:0] must be set to 100. opt6:4 = oscrange[2:0] oscillator range when the internal rc oscillator is not se lected (cksel1=1), these option bits (and cksel0) select the range of the resonator oscillator curren t source or the external clock source. opt 3:2 = sec[1:0] sector 0 size definition these option bits indicate the size of sector 0 according to ta b l e 9 4 . bit 1 = fmp_r read-out protection read-out protection, when selected provid es a protection against program memory content extraction and against write access to flash memory. erasing the option bytes when the fmp_r option is se lected will cause the whole memory to be erased first, and the device can be reprogrammed. refer to section 4.5 on page 27 and the st7 flash programming reference manual for more details. 0: read-out protection off 1: read-out protection on table 93. selection of the resonator oscillator range oscrange (1) 1. when the internal rc oscillator is selected, the cl ksel option bits must be kept at their default value in order to select the 256 clock cycle delay (see section 6.3 ). 210 typ. frequency range with resonator lp 1~2 mhz 0 0 0 mp 2~4 mhz 0 0 1 ms 4~8 mhz 0 1 0 hs 8~16 mhz 0 1 1 vlp 32.768 khz 1 0 0 external clock on osc1/clkin 1 0 1 reserved 1 1 0 external clock on pb1 1 1 1 table 94. configuration of sector size sector 0 size sec1 sec0 0.5k 00 1k 01 2k 10 4k 11
st7foxf1, ST7FOXK1, st7foxk2 device configuration and ordering information 213/226 bit 0 = fmp_w flash write protection this option indicates if the flash program memory is write protected. 0: write protection off 1: write protection on warning: when the flash write protection is selected, the program memory (and the option bit itself) can never be erased or programmed again. option byte 0 70 option byte 1 70 awu ck oscrange[2:0] sec 1 sec 0 fmp r fmp w ck sel1 ck sel0 res res res lvd wdg sw wdg halt default value 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1
device configuration and ordering information st7foxf1, ST7FOXK1, st7foxk2 214/226 13.2 device ordering information figure 93. st7foxf1/ST7FOXK1/st7foxk2 ordering information scheme st7fox failure analysis service for st7fox family devices, stmicroelectronics agrees to accept return of defective parts subject to the far (failure analysis report ) procedure only if the customer reject rate exceeds 0.35 % for each delivered batch. a batch is identified with a single trace code located on the top side marking. st7 fox k 1 b 6 tr family st7 microcontroller family memory size 1 = 4k 2 = 8k package b = dip m = so t = lqfp example: no. of pins f = 20 k = 32 sub-family fox temperature range 6 = -40 c to 85 c for a list of available options (e.g. memory size, package) and orderable part numbers or for fur- ther information on any aspect of this device, pl ease contact the st sales office nearest to you. shipping tr = tape and reel (available on lqfp32 and so20 packages only) blank = tube (dip and so packages) or tray (available on lqfp32 only)
st7foxf1, ST7FOXK1, st7foxk2 device configuration and ordering information 215/226 13.3 development tools development tools for the st7 microcontrollers include a complete range of hardware systems and software tools from stmicroelectronics and third-party tool suppliers. the range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 13.3.1 starter kits st offers complete, affordable starter kits . starter kits are complete hardware/software tool packages that include features and samples to help you quickly start developing your application. 13.3.2 development and debugging tools application development for st7 is supported by fully optimizing c compilers and the st7 assembler-linker toolchain, which are all seamlessly integrated in the st7 integrated development environments in order to facilit ate the debugging and fine-tuning of your application. the cosmic c comp iler is available in a free version that outputs up to 16kbytes of code. the range of hardware tools includes a full-featured stice emulator , the low-cost rlink and the st7-stick in-circuit debugger/programmer. these tools are supported by the st7 toolset from stmicroelectronics, which includes the stvd7 integrated development environment (ide) with high-level language debugger, editor, project manager and integrated programming interface. 13.3.3 programming tools during the development cycle, the stice emulator, the st7-stick and the rlink provide in-circuit programming capability for progra mming the flash microc ontroller on your application board. st also provides a low-cost dedicated in-circuit programmer and st7 socket boards, which provide all the sockets required for programming any of the devices in a specific st7 sub-family with any tool with in-cir cuit programming capability for st7. for production programming of st7 devices, st?s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment. 13.3.4 order codes for developm ent and programming tools ta bl e 9 5 below lists the ordering codes for the st7fox development and programming tools. for additional ordering codes for spare parts and accessories, refer to the online product selector at www.st.com/mcu.
device configuration and ordering information st7foxf1, ST7FOXK1, st7foxk2 216/226 13.4 st7 application notes table 95. development tool order codes mcu debugging and programming tool st socket boards st7foxf1 ST7FOXK1 st7foxk2 stx-rlink (1)(2) , st7-stick (3)(4) , stice emulator (5) 1. usb connection to pc. 2. available from st or from raisonance, www.raisonance.com. 3. add suffix /eu, /uk or /us for the power supply for your region. 4. parallel port connection to pc. 5. contact local st sales office for sales types. sbx-so20be, sbx-di8-20zz, sbx-dip32cd, and sbx-qp32bc socket boards (3) table 96. st7 application notes identification description application examples an1658 serial numbering implementation an1720 managing the read-out protection in flash microcontrollers an1755 a high resolution/precision thermometer using st7 and ne555 an1756 choosing a dali implementation strategy with st7dali an1812 a high precision, low cost, single supply adc for positive and negative input voltages example drivers an 969 sci communication between st7 and pc an 970 spi communicati on between st7 and eeprom an 971 i2c communication between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wakeup on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinuso?d) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sour ces management for st7 mcus an1045 st7 s/w implementation of i2c bus master
st7foxf1, ST7FOXK1, st7foxk2 device configuration and ordering information 217/226 an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 pwm management for bldc motor drives using the st72141 an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 emulated 16-bit slave spi an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer an1602 16-bit timing operations using st7262 or st7263b st7 usb mcus an1633 device firmware upgrade (dfu) implementation in st7 non-usb applications an1712 generating a high resolution sinewave using st7 pwmart an1713 smbus slave driver for st7 i 2 c peripherals an1753 software uart using 12-bit art an1947 st7mc pmac sine wave motor control software library general purpose an1476 low cost power supply for home appliances an1526 st7flite0 quick reference note an1709 emc design for st microcontrollers an1752 st72324 quick reference note product evaluation an 910 performance benchmarking an 990 st7 benefits vs industry standard an1077 overview of enhanced can c ontrollers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing table 96. st7 application notes (continued) identification description
device configuration and ordering information st7foxf1, ST7FOXK1, st7foxk2 218/226 an1103 improved b-emf detection for low speed, low voltage with st72141 an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st 72c254 applications to st72f264 an1604 how to use st7mdt1-train with st72f264 an2200 guidelines for migrating st7lite 1x applications to st7flite1xb product optimization an 982 using st7 with ceramic resonator an1014 how to minimize the st7 power consumption an1015 software techniques for improv ing microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1181 electrostatic discharge sensitive measurement an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1502 emulated data eeprom with st7 hd flash memory an1529 extending the current & volt age capability on the st7265 v ddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscillator an1605 using an active rc to wake up the st7lite0 from power saving mode an1636 understanding and minimizing adc conversion errors an1828 pir (passive infrared) detector using the st7flite05/09/superlite an1946 sensorless bldc motor control and bemf sampling methods with st7mc an1953 pfc for st7mc starter kit an1971 st7lite0 microcontrolled ballast programming and tools an 978 st7 visual develop software key debugging features an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain table 96. st7 application notes (continued) identification description
st7foxf1, ST7FOXK1, st7foxk2 device configuration and ordering information 219/226 an1039 st7 math utility routines an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ programming) an1446 using the st72521 emulator to debug an st72324 target application an1477 emulated data eeprom with xflash memory an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hd flash st7 mcus an1576 in-application programming (iap) drivers for st7 hd flash or xflash mcus an1577 device firmware upgrade (dfu) implementation for st7 usb applications an1601 software implementation for st7dali-eval an1603 using the st7 usb device firmware upgrade development kit (dfu-dk) an1635 st7 customer rom code release information an1754 data logging program for testing st7 applications via icc an1796 field updates for flash memory based st7 applications using a pc comm port an1900 hardware implementation for st7dali-eval an1904 st7mc three-phase ac inducti on motor control software library an1905 st7mc three-phase bldc motor control software library system optimization an1711 software techniques for compensating st7 adc errors an1827 implementation of sigma- delta adc with st7flite05/09 an2009 pwm management for 3-phase bldc motor drives using the st7fmc an2030 back emf detection during pwm on time by st7mc table 96. st7 application notes (continued) identification description
package mechanical data st7foxf1, ST7FOXK1, st7foxk2 220/226 14 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 94. 20-pin plastic small outline package, 300-mil width, package outline table 97. 20-pin plastic small outline package, 300-mil width, mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 2.35 2.65 0.0925 0.1043 a1 0.10 0.30 0.0039 0.0118 b 0.33 0.51 0.0130 0.0201 c 0.23 0.32 0.0091 0.0126 d 12.60 13.00 0.4961 0.5118 e 7.40 7.60 0.2913 0.2992 e 1.27 0.0500 h 10.00 10.65 0.3937 0.4193 h 0.25 0.75 0.0098 0.0295 0 8 0 8 l 0.40 1.27 0.0157 0.0500 number of pins n20 eh a a1 b e d c h x 45 l a
st7foxf1, ST7FOXK1, st7foxk2 package mechanical data 221/226 figure 95. 20-pin plastic dual in-line package , 300-mil width, package outline table 98. 20-pin plastic dual in-line package , 300-mil width, mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 5.33 0.2098 a1 0.38 0.0150 a2 2.92 3.30 4.95 0.1150 0.1299 0.1949 b 0.36 0.46 0.56 0.0142 0.0181 0.0220 b2 1.14 1.52 1.78 0.0449 0.0598 0.0701 c 0.20 0.25 0.36 0.0079 0.0098 0.0142 d 24.89 26.16 26.92 0.9799 1.0299 1.0598 d1 0.13 0.0051 e 2.54 0.1000 eb 10.92 0.4299 e1 6.10 6.35 7.11 0.2402 0.2500 0.2799 l 2.92 3.30 3.81 0.1150 0.1299 0.1500 number of pins n20 e1 d d1 b e a a1 l a2 c eb 11 10 1 20 b2
package mechanical data st7foxf1, ST7FOXK1, st7foxk2 222/226 figure 96. 32-pin plastic dual in-line package, shrink 400-mil width, package outline table 99. 32-pin plastic dual in-line package, shrink 400-mil width, mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 3.56 3.76 5.08 0.1402 0.1480 0.2000 a1 0.51 0.0201 a2 3.05 3.56 4.57 0.1201 0.1402 0.1799 b 0.36 0.46 0.58 0.0142 0.0181 0.0228 b1 0.76 1.02 1.40 0.0299 0.0402 0.0551 c 0.20 0.25 0.36 0.0079 0.0098 0.0142 d 27.43 28.45 1.0799 1.1201 e 9.91 10.41 11.05 0.3902 0.4098 0.4350 e1 7.62 8.89 9.40 0.3000 0.3500 0.3701 e 1.78 0.0701 ea 10.16 0.4000 eb 12.70 0.5000 ec 1.40 0.0551 l 2.54 3.05 3.81 0.1000 0.1201 0.1500 number of pins n32 d b2 b e a a1 a2 l e1 e ec c ea eb
st7foxf1, ST7FOXK1, st7foxk2 package mechanical data 223/226 figure 97. 32-pin low profile quad flat package (7x7), package outline table 100. 32-pin low profile quad flat package (7x7), package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 d 9.00 0.3543 d1 7.00 0.2756 e 9.00 0.3543 e1 7.00 0.2756 e 0.80 0.0315 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n32 h c l l1 b e a1 a2 a e e1 d d1
package mechanical data st7foxf1, ST7FOXK1, st7foxk2 224/226 14.1 thermal characteristics table 101. thermal characteristics symbol ratings value unit r thja package thermal resistance (junction to ambient) lqfp32 sdip32 so20 dip20 55 58 76 63 c/w t jmax maximum junction temperature (1) 1. the maximum chip-junction temperature is based on technology characteristics. 150 c p dmax power dissipation (2) 2. the maximum power dissipation is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an application can be defined by the user with the formula: p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation depending on the ports used in the application. 160 mw
st7foxf1, ST7FOXK1, st7foxk2 revision history 225/226 15 revision history table 102. document revision history date revision changes 15-oct-2007 1 initial release 23-oct-2007 2 interrupt mapping modified ( table 17 on page 58 and table 18 on page 59 ) section 12.8: emc (electromagnetic compatibility) characteristics on page 201 modified 23-nov-2007 3 added lvd function modified figure 5: st7foxf1/ST7FOXK1/st7foxk2 memory map on page 20 modified reset configuration for iccclk pin ( table 2: device pin description (32-pin packages) on page 16 modified table 3 on page 19 (added ain5 on pin n17) modified information on eix in figure 4: 20-pin so and dip package pinout on page 18 and table 3 on page 19 added break2 ( table 2: device pin description (32-pin packages) on page 16 and section 10.2: dual 12-bit autoreload timer on page 82 ) added pb5 in table 3 on page 19 modified note on spi in table 4: hardware register map on page 21 modified figure 44.: block diagram of input capture mode on page 90 modified figure 46.: long range input capture block diagram on page 91 modified note 4 in section 4.4: icc interface on page 25 modified figure 6: typical icc interface on page 26 modified figure 52: lite timer 2 block diagram on page 111 removed bits 2:0 in ltcsr1 register in : lite timer control/status register (ltcsr1) on page 115 modified figure 12: clock management block diagram on page 38 added rcc_csr in table 4: hardware register map on page 21 added customized rc calibration section modified section 10.2.3: functional description on page 84 (32 mhz references removed from pwm frequency and one pulse mode paragraphs) modified table 73: on-chip peripheral characteristics on page 193 modified section 10.7.1: introduction on page 173 modified section 13.3: development tools on page 215 modified section 13.2: device ordering information on page 214 07-feb-08 4 added dip20 package added lvd in figure 1: general block diagram on page 14 modified figure 93: st7foxf1/ST7FOXK1/st7foxk2 ordering information scheme on page 214 modified table 95: development tool order codes on page 216 modified table 101: thermal characteristics on page 224
st7foxf1, ST7FOXK1, st7foxk2 226/226 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com


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